Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS process. The measurements validate a substrate noise coupling macromodel that has been used to obtain the simulation results. The simulations and measurements also substantiate the...
This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics. The chip has been fabricated in a 130nm CMOS technology. To meet the power demands of body powered networks, a novel dual-path architecture capable of...
The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique...
A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
Delay insensitive asynchronous circuitry provides significant advantages with
respect to substrate noise due to localized switching. The differences between the
substrate noise from NULL Convention Logic (NCL) and traditional Clocked
Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
A variable gain, high linearity, low power baseband filter for WLAN applications is implemented in a 1.5 V 3 V 0.15 μm CMOS process. This fourth-order low-pass filter, which is introduced in the transmit channel as a reconstruction filter between the D/A converter and the mixer, has a measured cut-off...
Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
This thesis presents a low-energy application specific digital controller for a battery-free 2.4 GHz wireless sensor network (WSN) node. The digital controller has been designed and fabricated in a standard 0.13 μm CMOS and implements a simple protocol for WSNs. Techniques such as supply voltage reduction and power gating have...
This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
Modern sensor network applications are often implemented wirelessly in order to lessen installation costs and reduce deployment times. Unfortunately, these wireless sensor network (WSN) nodes must often rely on batteries or energy harvesting techniques in order to sustain their operation and supply the power needed to maintain communication within the...
For today’s ubiquitous portable devices, innovative integrated circuits with high performance
yet very low power are necessary. As these devices are used to communicate and sense real world signals in the environment, analog-to-digital converters (ADC) and systems are the key interface circuits needed to digitize the sensed information and they...
Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the battery life of the nodes. In this dissertation, two low power BFSK receiver architectures are proposed and verified with prototype implementations in silicion.
A 2.4...
Conventional Delta-Sigma analog-to-digital converters (ADCs) utilize operational transconductance amplifiers (OTAs) in their loop filter implementation followed by multi-bit voltage domain quantizers. As CMOS integrated circuit technology scales to smaller geometries, the minimum transistor length and the intrinsic gain of the transistors decrease. Moreover, with process scaling the voltage headroom decreases...
In April of 1997 it was pointed out at an NSF Engineering Education Innovators conference that “… education appears to ignore the need for connections and for integration – which should be at the core of an engineering education.” In order to solve this problem a group named ‘TekBotsTM’ was...