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Filtering by: Subject Amplifiers (Electronics) -- Noise Remove constraint Subject: Amplifiers (Electronics) -- Noise Advisor Fiez, Terri S. Remove constraint Advisor: Fiez, Terri S.

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  • A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

    Creator:
    Hazenboom, Duncan S.
    Abstract:
    Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
    Resource Type:
    Masters Thesis
    Full Text:
    - differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and

  • A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

    Creator:
    Ayers, James S.
    Abstract:
    An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
    Resource Type:
    Masters Thesis
    Full Text:
    bandwidth of the amplifier is high enough that the 10 MHz noise coupled to the amplifier will not be

  • Prediction of phase noise and jitter in ring oscillators

    Creator:
    Barton, Nathen
    Abstract:
    This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply...
    Resource Type:
    Masters Thesis
    Full Text:
    of Phase Noise and Jitter in Ring Oscillators. Abstract approved: Mayaram Tern S. Fiei This thesis

  • A substrate noise coupling model for lightly doped CMOS processes

    Creator:
    Sadate, Aline C.
    Abstract:
    This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
    Resource Type:
    Masters Thesis
    Full Text:
    used to predict noise coupling between an inverter and an amplifier, with both circuit simulations and

  • An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

    Creator:
    Arunachalam, Sasi Kumar S.
    Abstract:
    This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
    Resource Type:
    Masters Thesis
    Full Text:
    : An Efficient and Accurate Method of Estimating Substrate Noise Coupling in Heavily Doped Substrates

  • Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

    Creator:
    Hsu, Shu-ching
    Abstract:
    This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
    Resource Type:
    Masters Thesis
    Full Text:
    and Modeling of Substrate Noise Coupling for NMOS Transistors in Heavily Doped Substrates. Abstract

  • Design methodology for low-jitter phase-locked loops

    Creator:
    Bhagavatheeswaran, Shanthi, S.
    Abstract:
    This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
    Resource Type:
    Masters Thesis
    Full Text:
    used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise

  • Noise and Blocker Cancellation Techniques for Power and Area Efficient Wireless Receivers

    Creator:
    Pourbagheri, Saeed
    Abstract:
    The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique...
    Resource Type:
    Dissertation
    Full Text:
    usually provided by a power-hungry wideband low noise amplifier (LNA). Since the LNA is the first

  • Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems

    Creator:
    Zali Asl, Samira
    Abstract:
    For today’s ubiquitous portable devices, innovative integrated circuits with high performance yet very low power are necessary. As these devices are used to communicate and sense real world signals in the environment, analog-to-digital converters (ADC) and systems are the key interface circuits needed to digitize the sensed information and they...
    Resource Type:
    Dissertation
    Full Text:
    thesis, noise-shaping techniques are used to mitigate analog inaccuracies such as non-linearity and

  • An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

    Creator:
    Farahbakhshian, Farhad
    Abstract:
    An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
    Resource Type:
    Masters Thesis
    Full Text:
    and consumes 2.7mW. The measured phase noise is -136.2 dBc/Hz at a 3-MHz frequency offset. The ESDC