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Filtering by: Creator Nguyen, Vy T. Remove constraint Creator: Nguyen, Vy T. Advisor Lee, Ben Remove constraint Advisor: Lee, Ben

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  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    , C, G, M, R and T respectively by applying six-tap FIR filter as follows: ! b1 = (E " 5F

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    , Dr. Thinh Nguyen, and Dr. Shoichi Kimura for serving on my defense committee and for their helpful

  • Target-based coverage extension of 802.11 MANETs via constrained UAV mobility

    Creator:
    Johnson, Taylor N.
    Abstract:
    MANETs are known to be useful in situations where mobile nodes need to communicate and coordinate in dynamic environments with no access to fixed network infrastructure. However, connectivity problems can occur when sub-groups within a MANET move out of communication range from one another. The increasingly prolific use of UAVs...
    Resource Type:
    Masters Thesis
    Full Text:
    108A ve ra ge  E nd -­‐t o-­‐ En d   De la y   (m s)   #  of  ground  units   Delay   With

  • Power reduction of MPEG video decoding for mobile multimedia systems

    Creator:
    Lewis, James M.
    Abstract:
    The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed...
    Resource Type:
    Masters Thesis

  • Cost-Age-Time Data Organized Garbage Collection

    Creator:
    Lee, Dongjun
    Abstract:
    NAND flash based solid state drives (SSDs) require out-of-place updating due to the characteristics of flash memories. In addition, due to the mismatched granularity between read/write and erase operations, a cleaning policy involving garbage collection and wear leveling has to perform data migration incurring high overhead. Another challenge is that...
    Resource Type:
    Masters Thesis
    Full Text:
    ro lle r DRAM Request Queue Data Buffer Address Mappings Metadata H os t I nt er fa ce

  • Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor

    Creator:
    Browning, Adam W.
    Abstract:
    Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall...
    Resource Type:
    Masters Thesis
    Full Text:
    a value of True (T) for all the threads in Figure 4, indicating that all threads will have the

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis

  • Offloading of I/O transactions in current CPU architectures

    Creator:
    Larsen, Steen K.
    Abstract:
    IO transactions within a computer system have evolved along with other system components (i.e., CPU, memory, video) from programmed IO (PIO). In current mainstream systems (spanning from HPC to mobile) the IO transactions are CPU-centric descriptor-based DMA transactions. The key benefit is that slower IO devices can DMA write system...
    Resource Type:
    Dissertation
    Full Text:
    bene�t is that slower I/O devices can DMA write system receive tra�c to system memory and DMA read

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    Bose, Prof. Thinh Nguyen, Prof. Ronald A. Metoyer, Prof. Luca Lucchesse, and Prof. Keith Levien for

  • Spatial motion vector recovery in wireless high definition video transmission using H.264 over WLANs

    Creator:
    Gatimu, Kevin
    Abstract:
    Mobile devices are becoming more prevalent and complex. As a result, the wireless communication aspect of these devices is becoming increasingly significant. At the same time, video demands in terms of availability and quality are also on the uprise. High definition (HD) video is the standard of choice for meeting...
    Resource Type:
    Masters Thesis
    Full Text:
    conceal lost slices 2 and 4 p̂ = p T d B + p B d T + p L d R + p R d L d B + d T + d R + d