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Filtering by: Creator Clark, Robert G. Remove constraint Creator: Clark, Robert G. Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering

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  • Substrate noise coupling in ring oscillator-based phase locked loops

    Creator:
    Shreeve, Robert
    Abstract:
    In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Robert Shreeve for the degree of Master

  • An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

    Creator:
    Heiberg, Adam C.
    Abstract:
    A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
    Resource Type:
    Masters Thesis
    Full Text:
    to thank Tom, James, Napong, Farhad, Hector, Robert Batten, and Vikrant Arumugam for a number of

  • Design techniques for radiation hardened-phase locked loops

    Creator:
    Nemmani, Anantha Nag
    Abstract:
    Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit...
    Resource Type:
    Masters Thesis
    Full Text:
    energy required is 1.1eV. Similarly, it takes V G V G V G (a) (b) (c) Poly Oxide Bulk FIGURE 2.1

  • A substrate noise coupling model for lightly doped CMOS processes

    Creator:
    Sadate, Aline C.
    Abstract:
    This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
    Resource Type:
    Masters Thesis
    Full Text:
    am most grateful for that. I also thank Robert Shreeve for helping out with the testing. During the

  • An ultra low power frequency reference for timekeeping applications

    Creator:
    Oporta, Hector Ivan
    Abstract:
    An ultra low power crystal oscillator that provides a frequency reference for battery powered timekeeping applications is presented. An amplitude control circuit is employed to ensure that minimum current is consumed. A subthreshold voltage regulator provides a supply voltage for the oscillator with minimum current consumption. The oscillator and regulator...
    Resource Type:
    Masters Thesis
    Full Text:
    Panitantum, Vikrant Arumugam and Robert Batten for all of the good times we had in and outside of KEC3040

  • A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

    Creator:
    Held, Martin A.
    Abstract:
    A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
    Resource Type:
    Masters Thesis
    Full Text:
    there is a speedup of over 80 times with one-tenth the memory use is obtained with only a G percent

  • A nano-power wake-up circuit for RF energy harvesting wireless sensor networks

    Creator:
    Lindsley, Christopher J.
    Abstract:
    A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 36nA static current at 20°C and dissipates 2pJ of energy per conversion. The comparator comprises of...
    Resource Type:
    Masters Thesis
    Full Text:
    an undergraduate. Robert Batten, James Ayers, Thomas Brown, Napong Panitantum, Triet Le, Skyler

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    about substrate noise coupling. In addition, I would also like to thank Robert Batten for his help in

  • Ultra-low-energy transmitters for battery-free wireless sensor networks

    Creator:
    Panitantum, Napong
    Abstract:
    As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an ultra-low-energy WSN transmitter is developed to reduce the energy consumption of sensor nodes in WSNs. With an ultra-low-energy transceiver, it is possible to eliminate the...
    Resource Type:
    Dissertation
    Full Text:
    would also like to thank Thomas Brown, Triet Le, Robert Batten, Adam Heiberg, Steve Meliza, Chris

  • Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

    Creator:
    Hsu, Shu-ching
    Abstract:
    This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
    Resource Type:
    Masters Thesis
    Full Text:
    , Paul Hutchinson, Brian Owen, Ajit Sharma, and Robert Shreeve for all the help and cooperation on this