Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic radiation and require special design consideration. The purpose of this work is to explore methods of mitigating the effect of radiation in phase locked loop (PLL) circuits. Several voltage controlled oscillators (VCOs) and two complete PLLs are designed and...
The substrate noise injected by a stepped buffer circuit into two single-ended 1.5GHz low noise amplifiers is examined for a heavily doped 0.25µm CMOS process. The difference in the LNA noise rejection is characterized as a function of the size and placement of substrate contacts. The use of a resistive...
A digital implementation of a PLL has several advantages compared to its
analog counterpart. These include easy scalability with process shrink, elimination
of the noise susceptible analog control for a voltage controlled oscillator (VCO) and
the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL)
implementations have achieved...
Spacecrafts experience radiation in the course of their operation
and all electronic equipment on board these spacecrafts has to
be designed to withstand the effects of this radiation.
This thesis describes the effects of total ionization dose (TID)
and single event transients (SET) in phase-locked loops - an
important circuit...
The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in
environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
A Z-parameter based macromodel for characterizing the substrate noise coupling in a lightly doped substrate at low frequencies has been developed. The model is scalable with contact geometries and separation. The cross-coupling impedance between two contacts is modeled using an improved geometric mean distance formulation. This approach obviates the need...
This thesis presents a comparison of time-domain and frequency-domain algorithms for phase noise calculation in oscillators. Floquet theory provides the mathematical foundation for these calculations and the numerical methods employ perturbation projection vectors (PPVs). The PPVs are an estimate of an oscillator's sensitivity to noise.
The in-house circuit simulator SPICE3...
Delay insensitive asynchronous circuitry provides significant advantages with
respect to substrate noise due to localized switching. The differences between the
substrate noise from NULL Convention Logic (NCL) and traditional Clocked
Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
At frequencies exceeding 1-2 GHz, the substrate network models used in substrate coupling simulation must account for the reactive nature of the substrate. Unlike at low frequencies, where the purely resistive substrate models can be validated through DC resistance measurements, these high-frequency models, comprising reactive components, must be validated through...
This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...