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Filtering by: Alternative title ssim ORESU-Y-17-010 Remove constraint Alternative title ssim: ORESU-Y-17-010 Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya File Format application/pdf Remove constraint File Format: application/pdf

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  • An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

    Creator:
    Arunachalam, Sasi Kumar S.
    Abstract:
    This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 Analysis of simulation results . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.2

  • A test fixture and deembedding procedure for high-frequency substrate characterization

    Creator:
    Webb, Kyle M.
    Abstract:
    At frequencies exceeding 1-2 GHz, the substrate network models used in substrate coupling simulation must account for the reactive nature of the substrate. Unlike at low frequencies, where the purely resistive substrate models can be validated through DC resistance measurements, these high-frequency models, comprising reactive components, must be validated through...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . 17 LIST OF APPENDIX FIGURES Figure Page C-1 Photomicrograph of the complete test fixture

  • A substrate noise coupling model for lightly doped CMOS processes

    Creator:
    Sadate, Aline C.
    Abstract:
    This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
    Resource Type:
    Masters Thesis
    Full Text:
    ................................................... 17 3.3 Nwell Guards ....................................................... 23 3.4 Circuit Example

  • Computationally efficient substrate noise coupling estimation in lightly doped silicon substrates

    Creator:
    Srinivasan, Kavitha
    Abstract:
    A Z-parameter based macromodel for characterizing the substrate noise coupling in a lightly doped substrate at low frequencies has been developed. The model is scalable with contact geometries and separation. The cross-coupling impedance between two contacts is modeled using an improved geometric mean distance formulation. This approach obviates the need...
    Resource Type:
    Masters Thesis
    Full Text:
    2.8 Potential variation across the backplane for a 250µm thick substrate.............. 17 2.9

  • Oscillators and phase locked loops for space radiation environments

    Creator:
    Vandepas, Martin
    Abstract:
    Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic radiation and require special design consideration. The purpose of this work is to explore methods of mitigating the effect of radiation in phase locked loop (PLL) circuits. Several voltage controlled oscillators (VCOs) and two complete PLLs are designed and...
    Resource Type:
    Masters Thesis
    Full Text:
    . ........................................................ 17 3.4. Tuning curve for complimentary source LC VCO

  • Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs

    Creator:
    Sundaresan, Arathi
    Abstract:
    The substrate noise injected by a stepped buffer circuit into two single-ended 1.5GHz low noise amplifiers is examined for a heavily doped 0.25µm CMOS process. The difference in the LNA noise rejection is characterized as a function of the size and placement of substrate contacts. The use of a resistive...
    Resource Type:
    Masters Thesis
    Full Text:
    ....................................................................... 17 4.4 Noise injected by buffer 1 as seen at the output of LNA1

  • Comparison of time-domain and frequency-domain phase noise analyses

    Creator:
    Vytyaz, Igor
    Abstract:
    This thesis presents a comparison of time-domain and frequency-domain algorithms for phase noise calculation in oscillators. Floquet theory provides the mathematical foundation for these calculations and the numerical methods employ perturbation projection vectors (PPVs). The PPVs are an estimate of an oscillator's sensitivity to noise. The in-house circuit simulator SPICE3...
    Resource Type:
    Masters Thesis
    Full Text:
    ẏ = −A T (t)y cor- responding to Equation (2.5). Equation (2.22) implies that c1(t) is an

  • Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

    Creator:
    Hanken, Christopher
    Abstract:
    Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
    Resource Type:
    Masters Thesis
    Full Text:
    Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 Substrate Networks

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 Summary

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    . . . 17 2.7 Block diagram of a digital PLL. . . . . . . . . . . . . . . . . . . . . 23 3.1 Conventional