A duty-cycle controlled switched resistor is a tunable resistive element that uses pulse width modulation as the method of tuning. This thesis will describe the operation of switched resistors and propose several circuit architectures that are well suited to the use of switched resistors. These architectures include filters, mixers, and...
Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get...
This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired...
Analog-to-digital converters (ADCs) convert analog
continuous time signals into discrete time, digital format. One
precondition that must be met for conventional nyquist rate ADCs is
that the input signal must be suitably band-limited to an input
bandwidth less than the nyquist frequency. This mandates expensive
anti-alias filters which contribute to...
Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise...
To realize pipelined ADCs in deep-submicron processes, low voltage techniques
must be developed to work around problems created by limited supply voltages such as
the floating switch dead zone, reduced SNR, and reduced OpAmp performance.
This thesis analyzes standard and low voltage design issues for pipelined ADCs
and proposes a...
The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in
environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
A digital implementation of a PLL has several advantages compared to its
analog counterpart. These include easy scalability with process shrink, elimination
of the noise susceptible analog control for a voltage controlled oscillator (VCO) and
the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL)
implementations have achieved...
As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be- come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are...
Scaling of CMOS technology has progressed relentlessly for the past several
decades. In order for this unprecedented scaling to benefit the performance of
large digital systems, the communication bandwidth between integrated circuits
(ICs) must scale accordingly. However, interconnect technology does not scale as
aggressively, making communication between chips the major...
A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable.
The DPLL was found to reach a locked state under a limited...
Digital-to-analog converters (DACs) with wide dynamic range and high
linearity are required for high-end audio applications. A multi-bit delta sigma
audio DAC, using a novel gain-correction technique, is described in this thesis. For
widely varying on-chip RC time constant, the DAC gain can be accurately
controlled by the correction circuitry....
The demand for portable electronic systems and the continued
down-scaling of device dimensions resulted in rapid improvement in
the performance of integrated systems. Several low-voltage design
techniques have been proposed to operate analog circuits with sub-1V
supply. However, these techniques require higher power consumption
to achieve large dynamic range while...
This thesis presents a comparison of time-domain and frequency-domain algorithms for phase noise calculation in oscillators. Floquet theory provides the mathematical foundation for these calculations and the numerical methods employ perturbation projection vectors (PPVs). The PPVs are an estimate of an oscillator's sensitivity to noise.
The in-house circuit simulator SPICE3...
There is a large and growing market for portable consumer audio products
with very small size. As the size of these products is reduced, the area occupied
by batteries becomes significant and hence limits the number of batteries to one.
In order to build such small products, high levels of...
With the ever-increasing demand for portable devices used in applications
such as wireless communication, mobile computing, consumer electronics, etc.,
the scaling of the CMOS process to deep submicron dimensions becomes more
important to achieve low-cost, low-power and high-performance digital systems.
However, this downscaling also requires similar shrinking of the supply...
Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic radiation and require special design consideration. The purpose of this work is to explore methods of mitigating the effect of radiation in phase locked loop (PLL) circuits. Several voltage controlled oscillators (VCOs) and two complete PLLs are designed and...
Spacecrafts experience radiation in the course of their operation
and all electronic equipment on board these spacecrafts has to
be designed to withstand the effects of this radiation.
This thesis describes the effects of total ionization dose (TID)
and single event transients (SET) in phase-locked loops - an
important circuit...