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Filtering by: Creator Barros, A. M. Remove constraint Creator: Barros, A. M. Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku

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  • A 10 bit algorithmic A/D converter for a biosensor

    Creator:
    Rengachari, Thirumalai
    Abstract:
    This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter...
    Resource Type:
    Masters Thesis
    Full Text:
    . Title: A 10 Bit Algorithmic A/D Converter for a Bio-sensor Abstract approved: Gabor C. Temes and Un-Ku

  • Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters

    Creator:
    Sharma, Vivek
    Abstract:
    This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
    Resource Type:
    Masters Thesis
    Full Text:
    closed after this point for m cycles in which the stage resolves the current input, generates a residue

  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    . Alternatively, a continuous-time (CT) ∆ΣM can be used to decrease power consumption but has its own

  • Area efficient D/A converters for accurate DC operation

    Creator:
    Greenley, Brandon Royce
    Abstract:
    The design of mixed-signal integrated circuits has evolved from simple analog and digital circuits operating on the same silicon substrate to the point that now we have complete system on a chip solutions for communication systems. The levels of integration needed to remain cost effective in today's integrated circuit (IC)...
    Resource Type:
    Masters Thesis
    Full Text:
    (110 m x 94 pm), and only consumes 2.8 mW of power. In addition to the 10-bit DAC, a design is

  • A continuous time frequency translating delta Sigma Modulator

    Creator:
    Pulincherry, Anurag
    Abstract:
    This thesis presents a continuous time bandpass delta sigma modulator with frequency translation inside the delta sigma loop. The input IF signal is down converted to baseband after amplification by a low Q, wideband bandpass resonator. The down converted IF signal is digitized by a continuous time, second order lowpass...
    Resource Type:
    Masters Thesis
    Full Text:
    charging a capacitor and discharging in to the virtual ground of the integrator through a resistor. m cc

  • Low-voltage pipeline A/D converter

    Creator:
    Wu, Lei
    Abstract:
    Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their...
    Resource Type:
    Masters Thesis
    Full Text:
    Low-voltage pipeline A/D converter AN ABSTRACT OF THE THESIS

  • A stochastic time-to-digital converter for digital phase-locked loops

    Creator:
    Ok, Kerem
    Abstract:
    Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
    Resource Type:
    Masters Thesis
    Full Text:
    and sent for fabrication in a 0.35�m SOI CMOS process. System level simulations in MATLAB are

  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    presented on July 21, 2006. Title: Characterization of a Digital Phase Locked Loop and a Stochastic

  • A multi-bit delta sigma audio digital-to-analog converter

    Creator:
    Wang, Ruopeng
    Abstract:
    Digital-to-analog converters (DACs) with wide dynamic range and high linearity are required for high-end audio applications. A multi-bit delta sigma audio DAC, using a novel gain-correction technique, is described in this thesis. For widely varying on-chip RC time constant, the DAC gain can be accurately controlled by the correction circuitry....
    Resource Type:
    Dissertation
    Full Text:
    the delta sigma modulator and M is the number of bits of the internal DAC. Equation 2-8 shows that a

  • Digital implementation of a mismatch-shaping successive-approximation ADC

    Creator:
    Coe, Matthew T.
    Abstract:
    Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order Δ∑ loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis...
    Resource Type:
    Masters Thesis
    Full Text:
    , August 1995. 12. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio-independent algorithmic