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Filtering by: Committee Member Levien, Keith L. Remove constraint Committee Member: Levien, Keith L. Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku

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  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    276 277 278 279 Time (microseconds) C TR L W or d Figure 3.9 Phase error signal (top) and

  • A multi-bit delta sigma audio digital-to-analog converter

    Creator:
    Wang, Ruopeng
    Abstract:
    Digital-to-analog converters (DACs) with wide dynamic range and high linearity are required for high-end audio applications. A multi-bit delta sigma audio DAC, using a novel gain-correction technique, is described in this thesis. For widely varying on-chip RC time constant, the DAC gain can be accurately controlled by the correction circuitry....
    Resource Type:
    Dissertation
    Full Text:
    . Keithi L. Levien and Prof. Jimmy Yang for sitting on my committee. Their participation was of