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Filtering by: Conference section Thresholds/Monitoring/Sampling Remove constraint Conference section: Thresholds/Monitoring/Sampling Advisor Temes, Gabor C. Remove constraint Advisor: Temes, Gabor C. Degree Level Doctoral Remove constraint Degree Level: Doctoral

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  • Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling Rate

    Creator:
    He, Tao
    Abstract:
    Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
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    Dissertation
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    . Title: Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling

  • Design techniques for low power ADCs

    Creator:
    Yu, Wenhuan
    Abstract:
    This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise. In the calibration mode, the incremental ADC...
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    Dissertation
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    in single-sampling or double-sampling mode. Chopping with a fractal sequence is used to eliminate 1

  • Improved design techniques for analog and mixed circuits

    Creator:
    Nishida, Yoshio
    Abstract:
    Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice, temperature, etc. The bridge between these two worlds is one of key performance limitations among overall systems and it includes analog filters and data converters....
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    Dissertation
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    is a proposed correlated double- sampling technique for continuous analog filters. A circuit

  • A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs

    Creator:
    Wang, Yanchao
    Abstract:
    The sensors in real time data processing IoT devices require high resolution and sub-MHz data converters, usually implemented as Incremental ADCs due to the advantages of oversampling technique and low latency. In discrete time incremental (IDT) ADCs, the sampling switch non-linearity, charge injection degrade the resolution, and power hungry OPAMPs...
    Resource Type:
    Dissertation

  • High efficiency delta-sigma modulation data converters

    Creator:
    Lee, Kyehyung
    Abstract:
    Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common...
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    Dissertation
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    double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and

  • Switched Capacitor Circuit Techniques for High Performance CMOS Analog Circuits

    Creator:
    Kareppagoudr, Manjunath
    Abstract:
    Switched capacitor (SC) circuits are the main building blocks in many structures such as filters, data converters, sampling circuits and sampled-data amplifiers. The key challenge is to design such circuits which are the prime components of any IoT system with low power consumption without compromising on the performance. In this...
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    Dissertation
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    , sampling circuits and sampled-data amplifiers. The key challenge is to design such circuits which are the

  • Design techniques of high-performance switched capacitor circuits in the presence of component imperfections

    Creator:
    Huang, Yunteng
    Abstract:
    This thesis describes design techniques for high-performance switched-capacitor (SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of component imperfections, such as nonlinear op-amp voltage transfer characteristics, capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise. Various correlated-double-sampling (CDS) schemes are discussed,...
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    Dissertation
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    correlated-double-sampling (CDS) schemes are discussed, and some novel predictive CDS schemes are proposed

  • Improved design techniques for low-voltage low-power switched-capacitor delta-sigma modulators

    Creator:
    Grilo, Jorge
    Abstract:
    This dissertation investigates the constraints which arise when switched-capacitor (SC) delta-sigma modulators are designed for low-voltage operation, targeting also low power dissipation, and proposes methods of improving the performance and optimizing for low power dissipation. This is accomplished by identifying critical elements whose performance can lead to increased power dissipation,...
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    Dissertation
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    sampling is one of such techniques and is analyzed in detail. ©Copyright by Jorge Grilo June 27, 1997

  • Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits

    Creator:
    Sun, Tao
    Abstract:
    This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique...
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    Dissertation
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    correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such

  • High-accuracy circuits for on-chip capacitor ratio testing and sensor readout

    Creator:
    Wang, Bo, 1970-
    Abstract:
    The precise measurement of a capacitance difference or ratio in a digital form is very important for capacitive sensors, for CMOS process characterization as well as for the realization of precise switched-capacitor data converters, amplifiers and other circuits utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor ratio...
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    Dissertation
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    circuits are introduced, and the correlated-double-sampling (CDS) technique is used in the circuits to

  • Low-power double-sampled delta-sigma modulator for broadband applications

    Creator:
    Shen, Weilun
    Abstract:
    High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and...
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    Dissertation
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    : 1. Double sampled integrator to increase the effective over-sampling ratio. 2. Capacitor

  • Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

    Creator:
    Wang, Yan
    Abstract:
    Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations...
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    Dissertation
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    can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this

  • Active Noise Shaping Analog-to-Digital Data Converters

    Creator:
    Shi, Lukang
    Abstract:
    Successive-approximation-register (SAR) analog-to-digital converters are popular for medium accuracy, medium speed and low power applications, such as in biomedical applications. They have low latency and simple architecture compared with ΔΣ ADCs. This is because of SAR ADCs’ binary searching scheme. Furthermore, SAR ADCs can apply oversampling and noise shaping schemes...
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    Dissertation
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    DAC calibration was proposed and implemented. Correlated double sampling (CDS) and correlated level

  • Power Efficient Architectures for Low Noise Switched-Capacitor Filters and High Accuracy Analog-to-Digital Converters

    Creator:
    Payandehnia, Pedram
    Abstract:
    Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-defined radios and internet-of-things. In this dissertation, novel switched-capacitor filter and analog-to-digital converter (ADC) circuit configurations have been explored which are power efficient and are digital scaling friendly. First, a novel switched-capacitor low-pass filter architecture...
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    Dissertation
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    3.3 dB compared with that of a real-pole filter. The sampling rate of the filter is programmable from

  • Power Efficient Architectures for Medium-high Resolution Analog-to-Digital Converters

    Creator:
    Sadollahi, Mahmoud
    Abstract:
    Analog-to-digital converters are essential components to the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth require low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In this work power efficient ADCs for...
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    Dissertation
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    architecture was designed and implemented in 0.18 µm CMOS 2P6M process at sampling frequency of 160 MHz with

  • Low-power successive approximation analog to digital converter with digital calibration

    Creator:
    Li, Wei
    Abstract:
    IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
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    Dissertation
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    input is higher than the current comparison threshold ( 4 3 refV or 4 refV ), the SAR logic will

  • A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications

    Creator:
    Chen, Xuefeng
    Abstract:
    Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
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    Dissertation
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    …………………………………………………………………...4 2. OVERVIEW OF OVERSAMPLING �� ADC…………………………………………..5 2.1. Sampling and Quantization

  • High-performance delta-sigma analog-to-digital converters

    Creator:
    da Silva, Jose Barreiro
    Abstract:
    Multi-stage delta-sigma (ΔΣ) architectures, commonly known as MASH, are the preferred choice for analog-to-digital converters (ADCs) used in broadband communication applications, where high-resolution (above 14 bits) and high-bandwidth (several MHz) performances are required. Current state-of-the-art designs are capable of as much as 5-MS/s output data rates with 90-dB SNR. However,...
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    Dissertation
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    ................................................ 76 6.4 Noise gains from each sampling capacitor to the MASH ADC output 77 6.5 Relation between Cs11

  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
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    Dissertation
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    . .......................................... 5 Fig. 1-4. FoM versus sampling rate

  • Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

    Creator:
    Meng, Xin
    Abstract:
    Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
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    Dissertation
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    the sampling frequency and bandwidth of DT ΔΣ ADCs. Along with the increasing signal bandwidth, the