This thesis work proposes a low-power 12-bit digital-to-analog converter (DAC) designed in a 130nm process. The DAC to be presented is of a segmented design where the architecture is split into pipelined and thermometer coded segments. This allows for high linearity and low distortion while maintaining high speed and low...
This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively.
The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC...
With the growing demand for portable/consumer electronics, such as digital
audio/video (AV), the downscaling of device dimensions, which enables the
integration of an increasing number of transistors in a single chip, is mandatory.
This trend also continuously pushes the power supply voltage down to reduce the
power consumption and improve...
Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their...
This thesis describes compensation techniques for cascaded delta-sigma A/D
converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various
correlated-double-sampling (CDS) techniques are presented to reduce the effects of the
nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and
offset, and finite opamp gain, in SC circuits. A CDS technique...
In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction...
This thesis describes design techniques for high-performance switched-capacitor
(SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of
component imperfections, such as nonlinear op-amp voltage transfer characteristics,
capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise.
Various correlated-double-sampling (CDS) schemes are discussed,...
Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....