High performance multi-cell delta-sigma modulators are a preferred choice in applications which require programmability. Multi-cell delta-sigma modulators with M unit cells provide 10log10(M) SQNR improvement for the same thermal noise and bias power due to the uncorrelated quantization noises of the M unit ADCs. This concept is used in this...
In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is proposed, which can settle much faster than regular switch-capacitor integrators. A new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also introduced, which can effectively spread or shape the nonlinearity error of multi-bit DAC in the feedback path, thus improve the...
In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
The transition from second-generation (2G) to third-generation (3G) wireless cellular and cordless telephone systems requires multi-standard adaptability in a single RF receiver equipment. An important answer to this request is the use of Delta-Sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic range requirements for digital signal processing, and...
This thesis describes compensation techniques for cascaded delta-sigma A/D
converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various
correlated-double-sampling (CDS) techniques are presented to reduce the effects of the
nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and
offset, and finite opamp gain, in SC circuits. A CDS technique...
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts.
In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
The precise measurement of a capacitance difference or ratio in a digital form is
very important for capacitive sensors, for CMOS process characterization as well as for the
realization of precise switched-capacitor data converters, amplifiers and other circuits
utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor
ratio...
This thesis describes design techniques for high-performance switched-capacitor
(SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of
component imperfections, such as nonlinear op-amp voltage transfer characteristics,
capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise.
Various correlated-double-sampling (CDS) schemes are discussed,...
This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC...
Analog-to-digital converters are essential components to the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth require low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In this work power efficient ADCs for...