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Filtering by: Creator Li, Xin Remove constraint Creator: Li, Xin Advisor Temes, Gabor C. Remove constraint Advisor: Temes, Gabor C.

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  • Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

    Creator:
    Meng, Xin
    Abstract:
    Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
    Resource Type:
    Dissertation
    Full Text:
    Converters With Shifted Loop Delays AN ABSTRACT OF THE THESIS OF Xin Meng for the degree of Doctor

  • Low-power successive approximation analog to digital converter with digital calibration

    Creator:
    Li, Wei
    Abstract:
    IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
    Resource Type:
    Dissertation
    Full Text:
    AN ABSTRACT OF THE DISSERTATION OF Wei Li for the degree of Doctor of Philosophy in Electrical

  • Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits

    Creator:
    Sun, Tao
    Abstract:
    This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique...
    Resource Type:
    Dissertation
    Full Text:
    . 23 (a) The compensated integrator 00 I I _I 1 4)1 4)2 LI 4)3 1 1 (b) Clock phases VOW Figure

  • Low-power high-resolution delta-sigma ADC design techniques

    Creator:
    Wang, Tao
    Abstract:
    This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the...
    Resource Type:
    Dissertation
    Full Text:
    Young Kim, Michael Le, Tianwei Li, Tom Williams, Jade Dou, Bo Zhang, Hui Pan, Jun Cao, Jing Wang, Xin

  • Design techniques for successive approximation register analog-to-digital converters

    Creator:
    Tong, Tao
    Abstract:
    Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs...
    Resource Type:
    Masters Thesis
    Full Text:
    and byroads in research and life. I would also like to thank my group members, Tao Wang, Xin Meng

  • Linearity enhancement techniques for data converters

    Creator:
    Cao, Jinzhou
    Abstract:
    Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....
    Resource Type:
    Dissertation
    Full Text:
    brilliant and generous fellow graduate students. I especially thank Xin Meng for providing an ADC base

  • Low-power high-linearity digital-to-analog converters

    Creator:
    Kuo, Ming-Hung
    Abstract:
    In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
    Resource Type:
    Masters Thesis
    Full Text:
    Chen, Rishi Gupta, Young Ho Jung, Sang Hyeon Lee, Wei Li, Jiaming Lin, Xin Meng, Weilun Shen, Tao