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Filtering by: Creator Marias%2C Danielle E. Remove constraint Creator: Marias%2C Danielle E. Advisor Temes, Gabor C. Remove constraint Advisor: Temes, Gabor C.

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  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
    Resource Type:
    Dissertation
    Full Text:
    Synchronous and Asynchronous Clocking .................................................. 6 1.4.2 C-2C

  • Design techniques for low power ADCs

    Creator:
    Yu, Wenhuan
    Abstract:
    This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise. In the calibration mode, the incremental ADC...
    Resource Type:
    Dissertation
    Full Text:
    h e h (2-14) 14 where O is defined in (2-12) and e is [ ]T1 , ,1 ,1  . The objective

  • Low-voltage data converters

    Creator:
    Meng, Qingdong
    Abstract:
    With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve...
    Resource Type:
    Dissertation
    Full Text:
    introduced by the 1-bit truncator is given by e(k) = v(k) – y(k) (2.2) where v is the modulator

  • Low-voltage pipeline A/D converter

    Creator:
    Wu, Lei
    Abstract:
    Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their...
    Resource Type:
    Masters Thesis
    Full Text:
    tovcc switch network Cmoonl A to n cD I gnd gndl CSA S4A cD2 voutp S3 CS = 2C Cmoon 1

  • Linearity enhancement techniques for data converters

    Creator:
    Cao, Jinzhou
    Abstract:
    Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....
    Resource Type:
    Dissertation
    Full Text:
    and a DAC. Ignoring the DAC error E at the moment, the output (V) to input (U) transfer function in

  • Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits

    Creator:
    Sun, Tao
    Abstract:
    This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique...
    Resource Type:
    Dissertation
    Full Text:
    opamp gain A was 40 dB. The practical signal gain Gprac can be written as Gpraca-Gideagl e), where e is

  • Design techniques of high-performance switched capacitor circuits in the presence of component imperfections

    Creator:
    Huang, Yunteng
    Abstract:
    This thesis describes design techniques for high-performance switched-capacitor (SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of component imperfections, such as nonlinear op-amp voltage transfer characteristics, capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise. Various correlated-double-sampling (CDS) schemes are discussed,...
    Resource Type:
    Dissertation
    Full Text:
    op-amp gain A and the input-referred dc offset V, change it to Gid (1 + E) yin+ (1 + G ) V,, (2.3

  • High-linearity switched-capacitor circuits in digital CMOS technologies

    Creator:
    Yoshizawa, Hirokazu
    Abstract:
    In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction...
    Resource Type:
    Dissertation
    Full Text:
    ; (c) 2; (d) 3; (e) 4. For CAPOP = 0 and 4, the PMOSFET capacitance was constant in both accumulation

  • Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators

    Creator:
    Yang, Yaohua, 1969-
    Resource Type:
    Masters Thesis
    Full Text:
    input-output relationship of the modulator can be shown as y (nT) = u (nT T) + e (nT) e (nT T) (1.1

  • MOSFET-only predictive track and hold circuit

    Creator:
    Qiu, Xiangping
    Abstract:
    High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling...
    Resource Type:
    Masters Thesis
    Full Text:
    Computer Engineering HEAD of Department of E ec ical and Computer Engineering Dean of Graduate Sc of