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Filtering by: Creator Carilli, Patrick B. Remove constraint Creator: Carilli, Patrick B. Contributor advisor sim Fiez, Terri S. Remove constraint Contributor advisor sim: Fiez, Terri S.

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  • Silencer! : a tool for substrate noise coupling analysis

    Creator:
    Birrer, Patrick
    Abstract:
    This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
    Resource Type:
    Masters Thesis
    Full Text:
    THESIS OF Patrick Birrer for the degree of Master of Science in Electrical and Computer Engineering

  • Ultra-low power receivers for wireless sensor networks

    Creator:
    Ayers, James S.
    Abstract:
    In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed. A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show...
    Resource Type:
    Dissertation
    Full Text:
    . The entire receiver has an energy consumption of only 0.175 nJ/b while operating at 2 Mbps. c

  • Ultra-low energy digital logic controller design for wireless sensor networks

    Creator:
    Meliza, Stephen W.
    Abstract:
    Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital...
    Resource Type:
    Masters Thesis
    Full Text:
    , Patrick Chiang and Dr. Ethan Minot, for their time and support. I thank my professors, especially Roger

  • Ultra-low-energy transmitters for battery-free wireless sensor networks

    Creator:
    Panitantum, Napong
    Abstract:
    As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an ultra-low-energy WSN transmitter is developed to reduce the energy consumption of sensor nodes in WSNs. With an ultra-low-energy transceiver, it is possible to eliminate the...
    Resource Type:
    Dissertation
    Full Text:
    , (b) TelosB, (c) Tmote Sky, and (d) IRIS

  • Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

    Creator:
    Hsu, Shu-ching
    Abstract:
    This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
    Resource Type:
    Masters Thesis
    Full Text:
    research at OSU. Many thanks to my colleagues, Sirisha Adluri, James Ayers, Patrick Birrer, Husni Habal

  • A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

    Creator:
    Ayers, James S.
    Abstract:
    An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
    Resource Type:
    Masters Thesis
    Full Text:
    design process, Patrick Birrer and José Silva for their support in using cadence and other CAD tools

  • Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters

    Creator:
    Ranganathan, Sachin
    Abstract:
    A variable gain, high linearity, low power baseband filter for WLAN applications is implemented in a 1.5 V 3 V 0.15 μm CMOS process. This fourth-order low-pass filter, which is introduced in the transmit channel as a reconstruction filter between the D/A converter and the mixer, has a measured cut-off...
    Resource Type:
    Masters Thesis
    Full Text:
    , Zhimin, Volodymyr, Taras, Chenggang, Yutao, Shengjun, Kalyan, Vinay, Ravikanth, Ajit and Patrick for the

  • Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

    Creator:
    Sharma, Ajit
    Abstract:
    This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
    Resource Type:
    Masters Thesis
    Full Text:
    , Patrick Birrer, Brian Owens and Sirisha for all the help and cooperation on the substrate coupling

  • Design of sample and holds using CCDs in a standard CMOS process

    Creator:
    Ghatak, Kalyan Brata
    Abstract:
    The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer good performance at high speeds. This thesis presents the design of sample and hold circuits using charge-coupled device structures in a standard CMOS process. Three...
    Resource Type:
    Masters Thesis
    Full Text:
    Chennam, Taras Dudar, Patrick Birrer, Volodymyr Kratyuk, Yutao Hu, Edgar Constand, Nathen Barton

  • A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

    Creator:
    Held, Martin A.
    Abstract:
    A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
    Resource Type:
    Masters Thesis
    Full Text:
    , Sirisha Adluri, Brian Owens, Chengang Xu, Chee Boon (Steven) Law, Patrick Birrer, Matt MacClary, SasiKu