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Filtering by: Alternative title ssim Report no. 76-12 Remove constraint Alternative title ssim: Report no. 76-12 Committee Member Bose, Bella Remove constraint Committee Member: Bose, Bella Subject Computer architecture Remove constraint Subject: Computer architecture

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  • Cluster partitioning approaches to parallel Monte Carlo simulation on multiprocessors

    Creator:
    Ranawake, Udaya A.
    Abstract:
    We consider the parallelization of Monte Carlo algorithms for analyzing numerical models of charge transport used in semiconductor device physics. Parallel algorithms for the standard k-space Monte Carlo simulation of a three band model of bulk GaAs on hypercube multicomputers are first presented. This Monte Carlo model includes scattering due...
    Resource Type:
    Dissertation
    Full Text:
    Structure of the Parallel Monte Carlo Algorithm 12 2.4 Computing a Global Sum on the Hypercube 13 2.5

  • Optimizing the advanced encryption standard on Intel's SIMD architecture

    Creator:
    Godbole, Pankaj
    Abstract:
    The Advanced Encryption Standard (AES) is the new standard for cryptography and has gained wide support as a means to secure digital data. Hence, it is beneficial to develop an implementation of AES that has a high throughput. SIMD technology is very effective in increasing the performance of some cryptographic...
    Resource Type:
    Masters Thesis
    Full Text:
    Appendix 45 LIST OF FIGURES Figure Page 3.1 Key Expansion step Pseudo code 12 3.2 Selection of the

  • Scheduling system of affine recurrence equations by means of piecewise affine timing functions

    Creator:
    Mui, Lap K.
    Abstract:
    Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
    Resource Type:
    Masters Thesis
    Full Text:
    Figure 11 DG for u showing flow of data u 46 Figure 12 DG for u showing flow of data v 46 Figure 13

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 Loop Level Selection . . . . . . . . . . . . . . . . . . . . . . 12 2.3 The Cascadia