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Filtering by: Creator Spyridakis, Dimitri E. Remove constraint Creator: Spyridakis, Dimitri E. Committee Member Forbes, Leonard Remove constraint Committee Member: Forbes, Leonard Decade 2000-2009 Remove constraint Decade: 2000-2009

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  • Leakage power minimization by considering self-bias transistor and pin reordering technique

    Creator:
    Gopalakrishnan, Harish
    Abstract:
    Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold current. Minimizing leakage is gaining increasing importance along with other critical design aspects primarily due to the growing demand for portable battery-operated electronic devices...
    Resource Type:
    Masters Thesis
    Full Text:
    Discharge Figure 5: Load capacitor (dis)charge current and voltage [2] 11 EDD and E can be derived by