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Filtering by: DOI https://doi.org/10.1128/JB.01223-13 Remove constraint DOI: https://doi.org/10.1128/JB.01223-13 Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping Committee Member Temes, Gabor Remove constraint Committee Member: Temes, Gabor

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  • Design of a low jitter digital PLL with low input frequency

    Creator:
    Jung, Seokmin
    Abstract:
    Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog...
    Resource Type:
    Masters Thesis
    Full Text:
    ........................................................ 13 2.8 DCO resolution tradeoff – DAC resolution vs. DCO tuning range

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    . Opamp Reset Switching Technique (ORST) . . . . . . . . . . . . . . 13 2.2.6. Switched-RC Technique

  • Design techniques for low-voltage and low-power analog-to-digital converters

    Creator:
    Ahn, Gil Cho
    Abstract:
    With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4. Switched-Opamp Technique

  • Automated verilog-to-layout synthesis of ADCs using custom analog cells

    Creator:
    Waters, Allen
    Abstract:
    A procedure for automating the design and layout of analog-to-digital converters (ADCs) is presented. This procedure makes use of the existing synthesis and place-and-route tools that are common in digital circuit design. A method for adding rudimentary analog cells to the standard library is described, allowing the designer to synthesize...
    Resource Type:
    Dissertation
    Full Text:
    Synthesized Analog Blocks . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 Synthesized Stochastic

  • Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

    Creator:
    Guerber, Jon
    Abstract:
    In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
    Resource Type:
    Dissertation
    Full Text:
    ............................................................................... 13 2.3 THE MCS SAR

  • Data driven optimization in SAR ADC

    Creator:
    Leung, Jerry
    Abstract:
    Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques have been adopted to process signals with low activity periods, such as biomedical and industrial sensors. Prior work used least- significant bit first quantization (LSBFQ)...
    Resource Type:
    Masters Thesis
    Full Text:
    -skipping LSBFQ operation: best case scenario . . . . . . . . . . 13 2.12 Bit-Skipping LSBFQ measured

  • Low noise clocking for high speed serial links

    Creator:
    Brownlee, Merrick
    Abstract:
    As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be- come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are...
    Resource Type:
    Dissertation
    Full Text:
    transmit jitter on eye opening and (b) eye dia- gram before and after transmit jitter. 13 3.1 Charge

  • Dual referencing guidelines to minimize power delivery noise coupling

    Creator:
    Mark, Shannon
    Abstract:
    Dual referencing has been garnering a lot of attention in the power integrity community, specifically in the voltage mode driver application because it shows a lower overall power delivery noise (PDN) compared to other signal referencing types. Additionally, the increasing push to drive down package and board manufacturing costs is...
    Resource Type:
    Masters Thesis
    Full Text:
    ) …………………………………………….27 Figure 13: Power Insertion loss – Experiment 1 (S12) ………………………………………..27 Figure 14: Signal

  • Design techniques for low-power multi-GS/s analog-to-digital converters

    Creator:
    Jiang, Tao
    Abstract:
    Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...
    Resource Type:
    Dissertation
    Full Text:
    ..................................................................... 13 2.2. 2.2.1. Flash Architecture