Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques have been adopted to process signals with low activity periods, such as biomedical and industrial sensors. Prior work used least- significant bit first quantization (LSBFQ) to conserve capacitor switching energy and comparator decisions (bitcycles).
This work improves on the published least significant bit (LSB) first successive approximation ADC by restructuring its algorithm for further energy efficient switching, lowering its bitcycle range, and extending its range of applications. For target applications, these proposed solutions will outperform the bit-skipping LSBFQ and the merged capacitor switching (MCS) SAR, the most energy-efficient traditional most significant bit (MSB) first SAR.