High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most...
Detection of xenon radioisotopes (radioxenons) has proven to be an important method for detecting nuclear explosions and is particularly well suited for detecting undeclared underground testing. The radioxenon isotopes ¹³¹mXe (t₁/₂ = 11.934 d), ¹³³mXe (t₁/₂ = 2.19 d), ¹³³Xe (t₁/₂ = 5.243 d) and ¹³⁵Xe (t₁/₂ = 9.14 h)...
For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
Multi-stage delta-sigma (ΔΣ) architectures, commonly known as MASH, are the preferred choice for analog-to-digital converters (ADCs) used in broadband communication applications, where high-resolution (above 14 bits) and high-bandwidth (several MHz) performances are required. Current state-of-the-art designs are capable of as much as 5-MS/s output data rates with 90-dB SNR. However,...
Short-range wireless communications continually attract interest from both industry and academia, and it is changing our life in every aspect in the last decade. The design of wireless transceivers is the bottleneck for variety applications, due to RF modeling inaccuracy, stringent FCC regulations over the transmitted power spectrum, interference, multi-path...
A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
Dual referencing has been garnering a lot of attention in the power integrity community, specifically in the voltage mode driver application because it shows a lower overall power delivery noise (PDN) compared to other signal referencing types. Additionally, the increasing push to drive down package and board manufacturing costs is...
This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the...
Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....