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Filtering by: DOI 10.5194/hess-19-293-2015 Remove constraint DOI: 10.5194/hess-19-293-2015 Committee Member Liu, Huaping Remove constraint Committee Member: Liu, Huaping

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  • Power Efficient Architectures for Low Noise Switched-Capacitor Filters and High Accuracy Analog-to-Digital Converters

    Creator:
    Payandehnia, Pedram
    Abstract:
    Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-defined radios and internet-of-things. In this dissertation, novel switched-capacitor filter and analog-to-digital converter (ADC) circuit configurations have been explored which are power efficient and are digital scaling friendly. First, a novel switched-capacitor low-pass filter architecture...
    Resource Type:
    Dissertation
    Full Text:
    the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on November 19

  • An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

    Creator:
    Heiberg, Adam C.
    Abstract:
    A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
    Resource Type:
    Masters Thesis
    Full Text:
    Master of Science in Electrical and Computer Engineering presented on November 19, 2008. Title: An

  • An ultra low power frequency reference for timekeeping applications

    Creator:
    Oporta, Hector Ivan
    Abstract:
    An ultra low power crystal oscillator that provides a frequency reference for battery powered timekeeping applications is presented. An amplitude control circuit is employed to ensure that minimum current is consumed. A subthreshold voltage regulator provides a supply voltage for the oscillator with minimum current consumption. The oscillator and regulator...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Reference voltage

  • Semi-digital PLL architecture for ultra low bandwidth applications

    Creator:
    George, Edmond
    Abstract:
    Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area occupied by the large loop filter capacitor and resistor in a low bandwidth PLL design makes the realization of traditional charge-pump PLL architecture impractical on...
    Resource Type:
    Masters Thesis
    Full Text:
    value, it is actively pulled to 19 the maximum value and a digital bit is reset to 0 thus turning

  • Linearity enhancement techniques for data converters

    Creator:
    Cao, Jinzhou
    Abstract:
    Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....
    Resource Type:
    Dissertation
    Full Text:
    Electrical and Computer Engineering presented on March 18, 2015. Title: Linearity Enhancement

  • High-Resolution mm-wave Digitally Controlled Oscillator in CMOS

    Creator:
    Wang, Yunqi
    Abstract:
    All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to address a range of applications and low phase noise requirements. In this thesis, novel resonator structures with ne capacitance/inductance switching...
    Resource Type:
    Masters Thesis
    Full Text:
    Master of Science in Electrical and Computer Engineering presented on November 23rd, 2015. Title: High

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    12, 2015. Title: The Architecture of a Reusable Built-In Self-Test for Link Training, IO and

  • A 5 GHz Wi-Fi Receiver Front End with 4x80 MHz Channels for a High Accuracy Indoor Localization System

    Creator:
    Gray, Kyle L.
    Abstract:
    The ability to accurately locate people and objects indoors will enable opportunities for control and automation of indoor environments. Current indoor localization solutions require dedicated hardware which must be custom tailored to each application. There are large technological, societal, and economic benefits in developing a more general purpose system that...
    Resource Type:
    Masters Thesis
    Full Text:
    degree of Master of Science in Electrical and Computer Engineering presented on November 30, 2015

  • Dynamic Methods to Improve Streaming of H.264 HD Video Over 802.11 Wireless Networks

    Creator:
    Sinky, Mohammed H.
    Abstract:
    Wireless High Definition Video Transmission (WHDVT) over 802.11-based networks enjoys widespread deployment among today's multimedia solutions. Examples include Intel® Wireless Display and Apple Airplay®, to name a few. In these systems, peer-to-peer networks are established over which H.264-encoded video is transported wirelessly to be decoded and played back at the...
    Resource Type:
    Dissertation
    Full Text:
    Philosophy in Electrical and Computer Engineering presented on May 21, 2015. Title: Dynamic Methods to

  • Automated verilog-to-layout synthesis of ADCs using custom analog cells

    Creator:
    Waters, Allen
    Abstract:
    A procedure for automating the design and layout of analog-to-digital converters (ADCs) is presented. This procedure makes use of the existing synthesis and place-and-route tools that are common in digital circuit design. A method for adding rudimentary analog cells to the standard library is described, allowing the designer to synthesize...
    Resource Type:
    Dissertation
    Full Text:
    degree of Doctor of Philosophy in Electrical and Computer Engineering presented on March 5, 2015. Title