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Filtering by: Creator Chen, Jiaming Remove constraint Creator: Chen, Jiaming Committee Member Moon, Un-Ku Remove constraint Committee Member: Moon, Un-Ku

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  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
    Resource Type:
    Dissertation
    Full Text:
    AN ABSTRACT OF THE DISSERTATION OF Jiaming Lin for the degree of Doctor of Philosophy in

  • Design techniques for successive approximation register analog-to-digital converters

    Creator:
    Tong, Tao
    Abstract:
    Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs...
    Resource Type:
    Masters Thesis
    Full Text:
    , Wenhuan Yu, Yan Wang, Ming Hung Kuo, Jeong Seok Chae, Sang Hyeon Lee, Jinzhou Cao, Jiaming Lin

  • Design techniques for low-power electrical and optical serial link receivers

    Creator:
    Bai, Rui
    Abstract:
    As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links...
    Resource Type:
    Dissertation
    Full Text:
    Research Group during my internship. I thank Marco Fiorentino and Chin-Hui Chen at HP Labs, John Calvin

  • Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling Rate

    Creator:
    He, Tao
    Abstract:
    Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
    Resource Type:
    Dissertation
    Full Text:
    Dr. Chia-Hung Chen and Dr. Yi Zhang. In addition to their solid technical expertise, they also

  • Low-power high-linearity digital-to-analog converters

    Creator:
    Kuo, Ming-Hung
    Abstract:
    In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
    Resource Type:
    Masters Thesis
    Full Text:
    Chen, Rishi Gupta, Young Ho Jung, Sang Hyeon Lee, Wei Li, Jiaming Lin, Xin Meng, Weilun Shen, Tao

  • Wideband and high accuracy delta sigma modulation data converter

    Creator:
    Jung, Youngho
    Abstract:
    Nowadays, needs for wideband and high accuracy analog-to-digital converter are increasing rapidly in manifold applications such as wireless communication, digital video and other consumer electronics. Besides, low power consumption is required to have longer battery life in portable systems. CMOS technology scaling and innovative modulator topology make the implementation much...
    Resource Type:
    Dissertation
    Full Text:
    Yu, Yan Wang, Weilun Shen, Tong Tao, Wang Tao, Wei Li, Po-Yao Ke, Jiaming Lin, Chia-Hung Chen

  • Design techniques for high-performance digital PLLs and CDRs

    Creator:
    Yin, Wenjing
    Abstract:
    Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged...
    Resource Type:
    Dissertation
    Full Text:
    discussions and great helps on my research. Many thanks to the friendship of Kangmin Hu, Ronghua Ni, Chen

  • Performance enhancement techniques for low power digital phase locked loops

    Creator:
    Elshazly, Amr
    Abstract:
    Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate...
    Resource Type:
    Dissertation
    Full Text:
    Pawlowski, Joe Crop, Robert Pawlowski, Jiaming Lin, Omar Alsaleh, Rui Bai, and Behrouz Behmardi. Thanks to