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Filtering by: Creator Kirinicich, A. R. Remove constraint Creator: Kirinicich, A. R. Committee Member Nguyen, Thinh Remove constraint Committee Member: Nguyen, Thinh Decade 2000-2009 Remove constraint Decade: 2000-2009

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  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee This thesis presents a novel methodology that enables power efficient video

  • A high power emulation of a wind farm

    Creator:
    Lalla, Chelsea
    Abstract:
    As more wind farms are connected to the grid, the variable nature of wind energy begins to influence grid stability. Energy storage could help smooth the variable nature of wind energy. Laboratory demonstration and exploration of the interaction between different energy storage devices and wind energy could help improve and...
    Resource Type:
    Masters Thesis
    Full Text:
    comparing input and output measurements. The data in figure 3.3 have an R squared value of 99% for a

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    choose ready instructions to issue by way of a ‘request’ system, where instructions with both R bits

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    Parallel Loops AN ABSTRACT OF THE DISSERTATION OF David A. Zier for the degree of Doctor of Philosophy

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    Computer Engineering presented on March 6, 2006. Title: Asymmetric Clustering Using a Register Cache

  • A channelized digital receiver design for UWB sytems in a multipath indoor environment

    Creator:
    Chang, Yuhao
    Abstract:
    This thesis presents a channelized digital receiver design for UWB sytems in a multipath indoor environment. The UWB technology has been used for commercial and military purposes due to a number of advantages such as low-power consumption, noise-like and carrier free. The energy of UWB signal is spread over a...
    Resource Type:
    Masters Thesis
    Full Text:
    A channelized digital receiver design.doc 1 AN ABSTRACT OF THE

  • Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor

    Creator:
    Browning, Adam W.
    Abstract:
    Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall...
    Resource Type:
    Masters Thesis
    Full Text:
    the current instruction. If the R-bit is cleared, then a speculative thread cannot use the value

  • A genetic algorithm for the vehicle routing problem with heterogeneous vehicles from multiple depots, allowing multiple visits

    Creator:
    Lim, Hyunpae
    Abstract:
    In the thesis, an application of a genetic algorithm (GA) is considered to solve the vehicle routing problem (VRP) which involves heterogeneous vehicles to serve known customer demands from multiple depots achieving the minimum delivery cost, where each customer must be satisfied by one or more visit(s), and each vehicle...
    Resource Type:
    Masters Thesis
    Full Text:
    called a binary tournament. A random number r is then generated between 0 and 1. If r < k, where k is a

  • Diversity combining ARQ over the m(> 2)-ary unidirectional channel

    Creator:
    Elarief, Noha
    Abstract:
    In diversity combining automatic repeat request (ARQ), erroneous packets are combined together forming a single, more reliable, packet. In this thesis, we give a diversity combining scheme for the m-ary unidirectional channel. A system using the given scheme with a t-unidirectional error detecting code is able to correct up to...
    Resource Type:
    Masters Thesis
    Full Text:
    make that decision depending upon both the syndrome and the value of the check digits; Let a = #0(c′r

  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    schemes. They have been considered in a variety of industry standards for the next generation