General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
Interconnection networks play important roles in designing high performance computers. Recently two new classes of interconnection networks based on the concept of Gaussian and Eisenstein-Jacobi integers were introduced. In this research, efficient routing and broadcasting algorithms for these networks are developed. Furthermore, constructing edge disjoint Hamiltonian cycles in Gaussian networks...
The amount of instruction level parallelism (ILP) that can be exploited depends
greatly on the size of the instruction window and the number of in-flight instructions
the processor can support. However, this requires a register file with a large set of
physical registers for renaming and multiple ports to provide...
New video-conference devices based on omnidirectional multi-camera systems have been emerging in the last few years. These devices require innovative and automated video quality assessment in the earlier stages of their design in order to guarantee competitive product development and quality monitoring. Current quality assessment techniques are not adequate since...
The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed...
This thesis presents a novel methodology that enables power efficient video decoding
in an embedded system based on MPSoC (Multiprocessor System on Chip). This
methodology is a physical combination of parallel processing which reduces power
consumption of processors by exploiting thread-level parallelism and Dynamic
Voltage Frequency Scaling (DVFS) that allows...
Transmission over wireless networks presents multiple technical challenges due to
noise, interference, fading, power constraints and bandwidth limitation. Different
solutions have been propposed to overcome these issues and some of them are
treated here. Cooperative diversity has been proposed as an implementation for
networks where terminals are restricted to using...
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
Dynamic multithreaded processors attempt to increase the performance of a single
sequential program by dynamically extracting threads from sources such as loop
iterations. The scheduling of instructions in such a processor plays a vital role in the
amount of thread level parallelism that can be extracted and thus the overall...
An n-bit Gray code is an ordered set of all 2n binary strings of length n. The
special property of this listing is that Hamming distance between consecutive vectors
is exactly 1. If the last and first codeword also have a Hamming distance 1 then the
code is said to...