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Filtering by: Creator Scheffer%2C Theodore C. Remove constraint Creator: Scheffer%2C Theodore C. Committee Member Nguyen, Thinh Remove constraint Committee Member: Nguyen, Thinh

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  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
    Resource Type:
    Dissertation
    Full Text:
    Synchronous and Asynchronous Clocking .................................................. 6 1.4.2 C-2C

  • Linearity enhancement techniques for data converters

    Creator:
    Cao, Jinzhou
    Abstract:
    Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....
    Resource Type:
    Dissertation
    Full Text:
    : ______________________________________________________ Gabor C. Temes Data converters are essential interface circuits between the analog

  • Low-power successive approximation analog to digital converter with digital calibration

    Creator:
    Li, Wei
    Abstract:
    IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
    Resource Type:
    Dissertation
    Full Text:
    time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS," ISSCC 2009, pp. 76–77, Feb. 2009. [1-10] M

  • Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

    Creator:
    Wang, Yan
    Abstract:
    Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations...
    Resource Type:
    Dissertation
    Full Text:
    : _____________________________________________________________________ Gábor C. Temes Pavan Kumar Hanumolu Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs

  • On edge disjoint Hamiltonian cycles in torus and Gaussian networks

    Creator:
    Alazemi, Fawaz M.
    Abstract:
    Many algorithms in parallel systems can be easily solved if we can generate a Hamiltonian cycle on the underly network. Finding Hamiltonian cycle is a well known NP-complete problem. For specific instances of regular graphs, such as Torus and Gaussian network, one can easily find Hamiltonian cycles. In this thesis,...
    Resource Type:
    Masters Thesis
    Full Text:
    Gaussian network G bn/2c α , for 1 ≤ 2r ≤ n < 2r+1. c©Copyright by Fawaz M. Alazemi December 4, 2014

  • Compensation method of the excess loop delay in continuous-time delta-sigma ADCs based on model matching approach

    Creator:
    Guo, Jia
    Abstract:
    Continues-Time (CT) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs) have one important constrain, namely the excess loop delay. Most previous excess lop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distribution random variable....
    Resource Type:
    Masters Thesis
    Full Text:
    2.10 Common DAC pulse types: (a) NRZ, (b) RZ (c) HRZ ................................. 17  Figure 2.11

  • Network coding in relay networks

    Creator:
    Alban, Eduardo
    Abstract:
    Transmission over wireless networks presents multiple technical challenges due to noise, interference, fading, power constraints and bandwidth limitation. Different solutions have been propposed to overcome these issues and some of them are treated here. Cooperative diversity has been proposed as an implementation for networks where terminals are restricted to using...
    Resource Type:
    Masters Thesis
    Full Text:
    propose a scheme for a wireless network using ideas based on network coding. c©Copyright by Eduardo

  • Deletions and Insertions of the Symbol 0 and Asymmetric/Unidirectional Error Control Codes for the L₁ Metric

    Creator:
    Alqwaifly, Nawaf
    Abstract:
    This work gives some theory and efficient design of binary block codes capable of controlling the deletions of the symbol “0” (referred to as 0-deletions) and/or the insertions of the symbol “0” (referred to as 0-insertions). This problem of controlling 0-deletions and/or 0-insertions (referred to as symmetric 0-errors) is shown...
    Resource Type:
    Dissertation
    Full Text:
    Code examplewithn= 5 and t = 1. Example of a1-Sy0EC/2-Sy0ED/AU0ED code C of length 5 with |C|= 14

  • Limited magnitude error control codes

    Creator:
    Elarief, Noha
    Abstract:
    A relatively new model of error control is the limited magnitude error over high radix channels. In this error model, the error magnitude does not exceed a certain limit known beforehand. In this dissertation, we study systematic error control codes for common channels under the assumption that the maximum error...
    Resource Type:
    Dissertation
    Full Text:
    i is added to the sequence if and only if 2i (mod q) /∈ S and @c j ∈ S such that i≡ 2c j (mod q

  • The Analysis of Hormone-dependent Transcription Factors and lncRNAs in Seeds by RNA Sequencing

    Creator:
    Sall, Khadidiatou
    Abstract:
    Seed dormancy is defined as the inability of viable seeds to germinate under conditionsotherwise favorable for germination. Dormancy provides a strategy for seeds to germinateat an appropriate time. Abscisic acid (ABA) is a major hormone involved in the regulationof seed dormancy. To elucidate the molecular mechanisms of dormancy, the twoexperimental...
    Resource Type:
    Dissertation
    Full Text:
    -coding developmental regulatory RNA FLC FLOWERING LOCUS C FR far-red FUS3 FUSCA3 GA