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Filtering by: Committee Member Levien, Keith L. Creator Geissenhainer, Erik D.

Characterization of a digital phase locked loop and a stochastic time to digital converter

Creator:

Geissenhainer, Erik D.

Abstract:

A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35Âµm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...

Resource Type:

Masters Thesis

Full Text:

276 277 278 279 Time (microseconds) C TR L W or d Figure 3.9 Phase error signal (top) and