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Filtering by: Creator Gopalakrishnan, Harish Degree Level Master's

Leakage power minimization by considering self-bias transistor and pin reordering technique

Creator:

Gopalakrishnan, Harish

Abstract:

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold current. Minimizing leakage is gaining increasing importance along with other critical design aspects primarily due to the growing demand for portable battery-operated electronic devices...

Resource Type:

Masters Thesis