Index Catalog // ScholarsArchive@OSU

Multithreaded virtual processor on DSM

Creator:: An, Ho Seok
Abstract:: Modern superscalar processors exploit instruction-level parallelism (ILP) by issuing multiple instructions in a single cycle because of increasing demand for higher performance in computing. However, stalls due to cache misses severely degrade the performance by disturbing the exploitation of ILP. Multiprocessors also greatly exacerbate the memory latency problem. In SMPs,...
Resource Type:: Masters Thesis

Architectural support for multithreading on a 4-way multiprocessor

Creator:: Kim, Gwang-Myung
Abstract:: The microprocessors will have more than a billion logic transistors on a single chip in the near future. Several alternatives have been suggested for obtaining highest performance with billion-transistor chips. To achieve the highest performance possible, an on-chip multiprocessor will become one promising alternative to the current superscalar microprocessor. It...
Resource Type:: Masters Thesis

Master/slave parallel processing

Creator:: Larsen, Steen K.
Abstract:: An 8 bit microcontroller slave unit was designed, constructed, and tested to demonstrate advantages and feasibility of master/slave parallel processing using conventional processors and relatively slow inter-processor communications. An 8 bit ISA bus controlled by an 80X86 is interfaced to a logic block that controls data flow to and from...
Resource Type:: Masters Thesis

A study of hardware/software multithreading

Creator:: Carlson, Ryan L.
Abstract:: As the design of computers advances, two important trends have surfaced: The exploitation of parallelism and the design against memory latency. Into these two new trends has come the Multithreaded Virtual Processor (MVP). Based on a standard superscalar core, the MVP is able to exploit both Instruction Level Parallelism (ILP)...
Resource Type:: Masters Thesis

CounterDataFlow architecture : design and performance

Creator:: Miller, Michael F., (Michael Frederic)
Abstract:: The counterflow pipeline concept was originated by Sproull and Sutherland to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making and localized clocking and data movement. We have taken these ideas and reformulated them into a substantially faster more scalable architecture that has the same distributed...
Resource Type:: Masters Thesis

Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization

Creator:: Gao, Hairong
Abstract:: Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm. A mixed-signal IC implementation has been chosen for...
Resource Type:: Masters Thesis

Memory optimization for a parallel sorting hardware architecture

Creator:: Beyer, Dale A.
Abstract:: Sorting is one of the more computationally intensive tasks a computer performs. One of the most effective ways to speed up the task of sorting is by using parallel algorithms. When implementing a parallel algorithm, the designer has to make several decisions. Among the decisions are the algorithm and the...
Resource Type:: Masters Thesis

Simulation studies of routing algorithms for multicomputer systems

Creator:: Choi, Jangmin
Abstract:: Efficient routing of messages is critical to the performance of multicomputers. Many adaptive routing algorithms have been proposed to improve the network efficiency; however, they can make only short-sighted decisions to choose a channel for message routing because of limited information about network condition. The short-sighted decisions may cause unnecessary...
Resource Type:: Masters Thesis

Interface design and system impact analysis of a message-handling processor for fine-grain multithreading

Creator:: Metz, David
Abstract:: There appears to be a broad agreement that high-performance computers of the future will be Massively Parallel Architectures (MPAs), where all processors are interconnected by a high-speed network. One of the major problems with MPAs is the latency observed for remote operations. One technique to hide this latency is multithreading....
Resource Type:: Masters Thesis

Automatic scheduling and dynamic load sharing of parallel computations on heterogeneous workstation clusters

Creator:: Jacob, Joseph, 1971-
Abstract:: Parallel computing on heterogeneous workstation clusters has proved to be a very efficient use of available resources, increasing their overall utilization. However, for it to be a viable alternative to expensive, dedicated parallel machines, a number of key issues need to be resolved. One of the major challenges of heterogeneous...
Resource Type:: Masters Thesis

Evaluation of scheduling heuristics for non-identical parallel processors

Creator:: Kuo, Chun-Ho
Abstract:: An evaluation of scheduling heuristics for non-identical parallel processors was performed. There has been limited research that has focused on scheduling of parallel processors. This research generalizes the results from prior work in this area and examines complex scheduling rules in terms of flow time, tardiness, and proportion of tardy...
Resource Type:: Masters Thesis

Fine-grain parallelism on sequential processors

Creator:: Kotikalapoodi, Sridhar V.
Abstract:: There seems to be a consensus that future Massively Parallel Architectures will consist of a number nodes, or processors, interconnected by high-speed network. Using a von Neumann style of processing within the node of a multiprocessor system has its performance limited by the constraints imposed by the control-flow execution model....
Resource Type:: Masters Thesis

Allocation of SISAL program graphs to processors using BLAS

Creator:: Raisinghani, Manoj H.
Abstract:: There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing of programs so as to specify all the available parallelism. The success rate of any of the known techniques is rather poor over all types...
Resource Type:: Masters Thesis

A library for doing polyhedral operations

Creator:: Wilde, Doran K.
Abstract:: Polyhedra are geometric representations of linear systems of equations and inequalities. Since polyhedra are used to represent the iteration domains of nested loop programs, procedures for operating on polyhedra can be used for doing loop transformations and other program restructuring transformations which are needed in parallelizing compilers. Thus a need...
Resource Type:: Masters Thesis

Program allocation for hypercube based dataflow systems

Creator:: Freytag, Vincent R.
Abstract:: The dataflow model of computation differs from the traditional control-flow model of computation in that it does not utilize a program counter to sequence instructions in a program. Instead, the execution of instructions is based solely on the availability of their operands. Thus, an instruction is executed in a dataflow...
Resource Type:: Masters Thesis

An experimental investigation of scheduling non-identical parallel processors with sequence-dependent set-up times and due dates

Creator:: Smith, Terrence A.
Abstract:: An experimental investigation of factors effecting scheduling a system of parallel, non-identical processors using a series of experimental designs was carried out. System variables included were processor capacities relationships, sequencing and assignment rules, job size, and product demand distributions. The effect of the variables was measured by comparing mean flow...
Resource Type:: Masters Thesis

Scheduling system of affine recurrence equations by means of piecewise affine timing functions

Creator:: Mui, Lap K.
Abstract:: Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
Resource Type:: Masters Thesis

The "Mobius Cube" : an interconnection network for parallel computation

Creator:: Larson, Shawn M.
Resource Type:: Masters Thesis

ScholarsArchive@OSU

Multithreaded virtual processor on DSM

Architectural support for multithreading on a 4-way multiprocessor

Master/slave parallel processing

A study of hardware/software multithreading

CounterDataFlow architecture : design and performance

Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization

Memory optimization for a parallel sorting hardware architecture

Simulation studies of routing algorithms for multicomputer systems

Interface design and system impact analysis of a message-handling processor for fine-grain multithreading

Automatic scheduling and dynamic load sharing of parallel computations on heterogeneous workstation clusters

Evaluation of scheduling heuristics for non-identical parallel processors

Fine-grain parallelism on sequential processors

Allocation of SISAL program graphs to processors using BLAS

A library for doing polyhedral operations

Program allocation for hypercube based dataflow systems

An experimental investigation of scheduling non-identical parallel processors with sequence-dependent set-up times and due dates

Scheduling system of affine recurrence equations by means of piecewise affine timing functions

The "Mobius Cube" : an interconnection network for parallel computation

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