Index Catalog // ScholarsArchive@OSU

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Creator:: Sharma, Ajit
Abstract:: This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
Resource Type:: Masters Thesis

Leakage power minimization by considering self-bias transistor and pin reordering technique

Creator:: Gopalakrishnan, Harish
Abstract:: Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold current. Minimizing leakage is gaining increasing importance along with other critical design aspects primarily due to the growing demand for portable battery-operated electronic devices...
Resource Type:: Masters Thesis

High-speed CMOS dual-modulus presalers for frequency synthesis

Creator:: Desikachari, Ranganathan
Abstract:: Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design high-speed building blocks which dissipate the lowest possible power, and to ac- complish this with the cheapest technology. The dual-modulus prescaler is one of the...
Resource Type:: Masters Thesis

High-performance low-power microprocessor circuits

Creator:: Hsu, Steven K.
Abstract:: This thesis will discuss two critical components of a digital system -- domino logic styles and flip-flops. In today's microprocessors, both domino logic and flip-flops are essential to high-performance and low-power design. Two new domino logic styles are presented and analyzed, Double Edge Triggered (DET) and Double Data Rate (DDR)...
Resource Type:: Masters Thesis

Design of sample and holds using CCDs in a standard CMOS process

Creator:: Ghatak, Kalyan Brata
Abstract:: The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer good performance at high speeds. This thesis presents the design of sample and hold circuits using charge-coupled device structures in a standard CMOS process. Three...
Resource Type:: Masters Thesis

Design of low power 2.4GHz CMOS LC balanced oscillators with low phase noise and large tuning range

Creator:: Seshan, Nilakantan
Abstract:: The design of two 2.4GHz CMOS LC balanced oscillators in the 0.25μm National BiCMOS process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequency offset of 500KHz from the 2.11GHz carrier, the measured phase noise is -101.9dBc/Hz for the NMOS oscillator...
Resource Type:: Masters Thesis

Design of current-mode track and hold circuits

Creator:: Chennam, Madhusudhan
Abstract:: A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-μm quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD)...
Resource Type:: Masters Thesis

Comparison and analysis of jitter in CMOS ring oscillators

Creator:: Natesan, Peroly
Abstract:: A comparison and analysis of jitter for five different architectures of ring oscillators using a novel simulation technique developed by Professor Forbes' group is presented. Ring oscillators have become an essential building block in many digital and synchronous communications system due to their integrated nature and are widely used in...
Resource Type:: Masters Thesis

Area efficiency improvement of CMOS charge pump circuits

Creator:: Perigny, Ryan
Abstract:: In this thesis, the literature relating to charge pump dc-dc converters and their uses is reviewed. Charge pumps are useful in many circuits, including low-voltage circuits, dynamic random access memory circuits, switched-capacitor circuits, EEPROM's and transceivers. The important issues relating to charge pump design are power efficiency, output voltage ripple...
Resource Type:: Masters Thesis

An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

Creator:: Özis, Hatice Dicle
Abstract:: A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for...
Resource Type:: Masters Thesis

A substrate noise coupling model for lightly doped CMOS processes

Creator:: Sadate, Aline C.
Abstract:: This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
Resource Type:: Masters Thesis

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

Creator:: Hazenboom, Duncan S.
Abstract:: Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
Resource Type:: Masters Thesis

ScholarsArchive@OSU

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Leakage power minimization by considering self-bias transistor and pin reordering technique

High-speed CMOS dual-modulus presalers for frequency synthesis

High-performance low-power microprocessor circuits

Design of sample and holds using CCDs in a standard CMOS process

Design of low power 2.4GHz CMOS LC balanced oscillators with low phase noise and large tuning range

Design of current-mode track and hold circuits

Comparison and analysis of jitter in CMOS ring oscillators

Area efficiency improvement of CMOS charge pump circuits

An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

A substrate noise coupling model for lightly doped CMOS processes

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

Limit your search

Academic Affiliation

Advisor

Commencement Year

Committee Member

Creator

Date

Decade

Degree Field

Degree Level

Degree Name

File Format

Language

License

Non-Academic Affiliation

Peer Reviewed

Resource Type

Rights Statement

Subject

Search Constraints

Search Results

Limit your search