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Filtering by: Creator Keller, R. A. Remove constraint Creator: Keller, R. A. Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering Language English [eng] Remove constraint Language: English [eng]

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  • Fundamental studies of atomic diffusion by computer simulation of atomic processes on the giga event scale and multiple PC's in parallel

    Creator:
    Zhang, Qiongshan
    Abstract:
    The classic treatment of diffusion by Einstein and by Chandrasekhar assumed conservative boundary conditions; mobile species were neither created nor destroyed on the sample surface. It is normal to assume that vacancies and host interstitials are created and annihilated on incoherent interfaces or free surfaces; i.e., these are assumed to...
    Resource Type:
    Masters Thesis
    Full Text:
    presence of an external force field, Eq. (2.2.18) is replaced by 16 ap a(1.KP) r, a2 n, at ax ax2 but

  • Design and simulation of a model for lymphocyte flow through single lymphnodes

    Creator:
    Heilig, Thomas
    Abstract:
    A compartmental model of lymphocyte circulation through a lymphnode is derived and simulated. The purpose of the model is to analyze experimental data and in turn design experimental plans from the analysis in order to obtain sufficient data for the organ-distributed immune response. The model will be used to predict...
    Resource Type:
    Masters Thesis
    Full Text:
    ;4 e r lj A compartmental model of lymphocyte circulation through a lymphnode is derived and

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    Energy = Wire Energy (a) R N R R R N 3-cycle 3-cycle 3-cycle 3-cycle Baseline NoC Delay >= 17

  • Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

    Creator:
    Pham, Hui En
    Abstract:
    Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Terri Fiez Karti Mayaram Analysis of substrate noise coupling has been performed for a 0.18µm

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    Efficient Simulation of Synchronous Digital Switching Noise in Systems on a Chip Abstract approved

  • Compartmental analysis of the immune system

    Creator:
    Lawrence, Karen
    Abstract:
    A compartmental model of the immune system is simulated. Chapter I discusses the importance of such a model, reviews past immune system models, and summaries the immunological theory the model is based upon. In Chapter II, the compartmental representation of the immune system is developed from immunological and physiological theory....
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Redacted for Privacy R. R. Mohleix A compartmental model of the immune system is simu- lated

  • A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

    Creator:
    Xiao, Ying
    Abstract:
    A novel switched-R-MOSFET-C input branch is proposed for low-voltage and high-linearity applications. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in gate voltage, and is therefore particularly suitable for low-voltage applications. The advantages of the...
    Resource Type:
    Masters Thesis
    Full Text:
    , 2004 . Title: A Tunable Duty-Cycle-Controlled Switched-R-MOSFET-C CMOS Filter for Low-Voltage and

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    . O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung, and R. Mooney, “A 20Gb/s Forwarded Clock

  • IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

    Creator:
    Liu,Yao
    Abstract:
    Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
    Resource Type:
    Dissertation
    Full Text:
    . A good candidate for the antenna substrate should have a small value of dielectric constant �r

  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee This thesis presents a novel methodology that enables power efficient video