The prevalence of Internet-of-Things (IoT) applications leads to an increasing focus on the design and optimization of sensor nodes. Battery lifetime and associated costs of battery replacement often limits the long term operation and viability of sensor nodes. RF wireless energy harvesting on the other hand can be appealing since...
This work presents the design and implementation of a low power phased-array receiver frontend at 28 GHz in 65 nm CMOS. The frontend incorporates a low- power low-noise amplifier(LNA) and a passive reflection-type phase shifter (RTPS) capable of providing 360° phase shift with 5-bit phase resolution and low loss variation....
All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to address a range of applications and low phase noise requirements. In this thesis, novel resonator structures with ne capacitance/inductance switching...
The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in...
The new CMOS folded source-coupled logic (FSCL)
technique intended for mixed-mode integrated circuits has
been designed. It has advantages over conventional CMOS
circuit in terms of reduced current spike, circuit delay,
logic flexibility, and layout density. A simple CPU
implemented in 2 μm CMOS technology with a 5.0 volt supply...
For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...
With increasing interest in current-mode analogue processing due to its high
performance properties such as speed, bandwidth and accuracy compared to voltage-mode
processing, new current-mode alternatives to various conventional circuit designs are
appearing. In this report, a novel circuit design to construct a fully-differential current-mode
operational amplifier ( OP-AMP )...
Computers using the tagged-token dataflow model are among the best candidates for delivering extremely high levels of performance required in the future. Instruction scheduling in these computers is determined by associatively matching data-bearing tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens with matching contexts are...
The design and implementation of Switched-Current (SI) ladder filters is
described. SI filters require only a standard digital CMOS process and the power
supply voltage requirement is low. SI circuits also can be potentially operated at
higher frequencies than Switched-Capacitor (SC) filters due to the low-impedance
wideband nodes of the...
A series of complex digital blocks have been designed and fabricated using the newly
developed current-mode differential CMOS logic family viz. the Folded Source-Coupled
Logic ( FSCL ). The main feature of this logic family is the low current spikes generated
during the switching transitions ( at least 2 orders...
Clock-feedthrough effects, channel-length modulation and device mismatch are
the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these
non-ideal effects are analyzed. A high-performance current mirror, namely regulated
cascode current mirror, which eliminates drain voltage variation problem is introduced.
By using this current mirror as a...
With advancements in CMOS technology, high speed analog circuits that were
traditionally implemented with discrete circuit components can now be made monolithically.
Antialiasing filters for video signals as well as signal conditioning filters in high
speed communication channels are examples of applications where high frequency integrated
circuits are now feasible....
High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling...
A negatively biased substrate has several advantages over a grounded substrate in CMOS
technology. The on-chip generation of this negative substrate bias has made chips easier
to use when only a single supply is preferred. This project demonstrates two types of
charge pump circuits used to generate negative voltages not...
Substrate switching noise is becoming a concern as integrated circuits get larger and speeds get faster. Mixed-mode integrated circuits are especially affected as the substrate noise interferes with sensitive analog circuits resulting in limited signal to noise ratios. This thesis serves to study the cause of the noise at the...
In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction...
Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power product(SPP). 32-bit CMOS adders are used as representative circuits to investigate a method of
reducing the SPP. The purpose of this thesis is to show...
Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major challenges facing circuit...
In recent years, there has been an extensive effort to develop low-cost implementations
of radio frequency integrated circuits for consumer applications. This thesis is a
research effort in the design and implementation of integrated RF CMOS Power Amplifiers
(PAs). A significant challenge in the implementation of RF CMOS ICs is...
Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low
cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA
is the inaccurate high-frequency noise model of the MOSFET implemented in circuit
simulators such as SPICE. Silicon-based monolithic inductors are another...
In this thesis, the literature relating to charge pump dc-dc converters and their uses is reviewed. Charge pumps are useful in many circuits, including low-voltage circuits, dynamic random access memory circuits, switched-capacitor circuits, EEPROM's and transceivers. The important issues relating to charge pump design are power efficiency, output voltage ripple...
This thesis will discuss two critical components of a digital system -- domino logic styles and flip-flops. In today's microprocessors, both domino logic and flip-flops are essential to high-performance and low-power design. Two new domino logic styles are presented and analyzed, Double Edge Triggered (DET) and Double Data Rate (DDR)...
A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-μm quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD)...
This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer good performance at high speeds. This thesis presents the design of sample and hold circuits using charge-coupled device structures in a standard CMOS process. Three...
The design of two 2.4GHz CMOS LC balanced oscillators in the 0.25μm National BiCMOS process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequency offset of 500KHz from the 2.11GHz carrier, the measured phase noise is -101.9dBc/Hz for the NMOS oscillator...
Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold current.
Minimizing leakage is gaining increasing importance along with other critical design aspects primarily due to the growing demand for portable battery-operated electronic devices...
The ability to integrate designs from board level, multi-chip modules to single process solutions is highly attractive in today's PC multimedia industry. Saving board area and chip count will decrease the production cost of personal computing hardware and increase profitability. The ability to integrate analog circuit capability and it's reference...
Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal
building blocks, especially...
Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
A comparison and analysis of jitter for five different architectures of ring oscillators using a novel simulation technique developed by Professor Forbes' group is presented. Ring oscillators have become an essential building block in many digital and synchronous communications system due to their integrated nature and are widely used in...
Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design high-speed building blocks which dissipate the lowest possible power, and to ac- complish this with the cheapest technology. The dual-modulus prescaler is one of the...
Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for performing similar operations. Register File (RF) arrays are located at the top...
A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for...
This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...