Index Catalog // ScholarsArchive@OSU

Identification of synchronous machine parameters

Creator:: Shaban, Ali Omar
Abstract:: The synchronous machine is an essential component of a power system and determination of its parameters accurately is an important task in securing adequate modes of operation through certain control strategies. An estimation technique based on the Powell algorithm was evaluated for the identification of these parameters on the basis...
Resource Type:: Dissertation
Full Text:: properties. IDENTIFICATION OF SYNCHRONOUS MACHINE PARAMETERS by All Omar Shaban A THESIS submitted to

New algorithms and architectures for arithmetic in GF(2[superscript m]) suitable for elliptic curve cryptography

Creator:: Rodríguez-Henríquez, Francisco
Abstract:: During the last few years we have seen formidable advances in digital and mobile communication technologies such as cordless and cellular telephones, personal communication systems, Internet connection expansion, etc. The vast majority of digital information used in all these applications is stored and also processed within a computer system, and...
Resource Type:: Dissertation
Full Text:: a generalized m = 193-bit binary Karat- suba multiplier .......................... 81 5.7

A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate

Creator:: Gupta, Shivani
Resource Type:: Masters Thesis
Full Text:: 1-mW, 14-bit EA A/D Converter with 10-KHz Conversion Rate Abstract approved- Stephen M. Goodnick

The Effectiveness of Using Robotics for Career Technology Education in a Middle School STE(A)M Course

Creator:: Bodle, Ernie
Abstract:: Using robotics in education allows students to become familiar with multiple topics in science, technology, engineering, and mathematics (STEM). With the use of robotic educational tools in the 8th – 12th grade classrooms, such as Sphero, Anki Cozmo, and Lego Mindstorms, few devices allow students to build the robots’ electrical...
Resource Type:: Masters Thesis
Full Text:: . Title: The Effectiveness of Using Robotics for Career Technology Education in a Middle School STE(A)M

Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

Creator:: Pham, Hui En
Abstract:: Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
Resource Type:: Masters Thesis
Full Text:: cases with a ground trace inductance of 13nH (light shading) and 1.5nH (dark shading), where M is the

Low-power high-performance 32-bit 0.5[u]m CMOS adder

Creator:: Shah, Parag Shantu
Abstract:: Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power product(SPP). 32-bit CMOS adders are used as representative circuits to investigate a method of reducing the SPP. The purpose of this thesis is to show...
Resource Type:: Masters Thesis
Full Text:: ) is a super set of Po(n). The most significant bit (MSB) of the right block (bit m) has a large fan

Accurate and efficient simulation of synchronous digital switching noise in system on a chip

Creator:: Habal, Husni
Abstract:: A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
Resource Type:: Masters Thesis
Full Text:: period to be substituted into the cell macro model. 12 If there are M inputs to a digital cell and

Energy efficient communication across on-chip wires in digital CMOS

Creator:: Postman, Jacob
Abstract:: For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
Resource Type:: Dissertation
Full Text:: , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

Creator:: Querbach, Bruce
Abstract:: The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
Resource Type:: Dissertation
Full Text:: . O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung, and R. Mooney, “A 20Gb/s Forwarded Clock

Power efficient H.264 video decoding in embedded multiprocessor

Creator:: Kim, Jihong
Abstract:: This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
Resource Type:: Masters Thesis
Full Text:: shows samples A-M (predictor) used to predict a 4x4 block. The samples have been previously encoded

ScholarsArchive@OSU

Identification of synchronous machine parameters

New algorithms and architectures for arithmetic in GF(2[superscript m]) suitable for elliptic curve cryptography

A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate

The Effectiveness of Using Robotics for Career Technology Education in a Middle School STE(A)M Course

Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

Low-power high-performance 32-bit 0.5[u]m CMOS adder

Accurate and efficient simulation of synchronous digital switching noise in system on a chip

Energy efficient communication across on-chip wires in digital CMOS

The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

Power efficient H.264 video decoding in embedded multiprocessor

Limit your search

Academic Affiliation

Advisor

Commencement Year

Committee Member

Creator

Contributor

Date

Decade

Degree Field

Degree Level

Degree Name

File Format

Language

License

Non-Academic Affiliation

Peer Reviewed

Resource Type

Rights Statement

Subject

Search Constraints

Search Results

Limit your search