Search Constraints

Start Over
Filtering by: Creator Sowers, Todd A. Remove constraint Creator: Sowers, Todd A. Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering

Search Results

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

  • Analysis and optimal sizing of an energy storage system for wind farm applications

    Creator:
    Yen, Zuan Z.
    Abstract:
    Modern wind energy is the technology of choice with a short payback period for increasing renewable energy portfolios. Bonneville Power Administration (BPA), a United States power authority in the Pacific Northwest expects to increase their wind energy capacity from 2,000 megawatts to 6,000 megawatts within the next five years. Currently...
    Resource Type:
    Masters Thesis
    Full Text:
    : Ted K. Brekken Modern wind energy is the technology of choice with a short payback period for

  • A simulation and architectural study of TCP/IP

    Creator:
    Becker, Bridget A.
    Abstract:
    This paper discusses current network technologies and protocols and presents a simulation study of the most common networking protocol used today, TCP/IP. The TCP/IP protocol stack has many inherent problems that will be shown through this simulation study. Using the SimpleScalar Toolset, the significance of the data copying and checksumming...
    Resource Type:
    Masters Thesis
    Full Text:
    A simulation and architectural study of TCP/IP AN ABSTRACT

  • Secure Data Analytics under Data Integrity Attacks

    Creator:
    De Silva, Shashini A.
    Abstract:
    There has been tremendous growth in using data analytic and machine learning algorithms to make critical decisions, such as in the national power grid, healthcare operations, and autonomous vehicles. Employing data analytic for decision-making allows cyber attackers to manipulate the decisions of these algorithms through data falsification. Hence, the trustworthiness...
    Resource Type:
    Dissertation
    Full Text:
    AN ABSTRACT OF THE DISSERTATION OF Shashini A. De Silva

  • A study of hardware/software multithreading

    Creator:
    Carlson, Ryan L.
    Abstract:
    As the design of computers advances, two important trends have surfaced: The exploitation of parallelism and the design against memory latency. Into these two new trends has come the Multithreaded Virtual Processor (MVP). Based on a standard superscalar core, the MVP is able to exploit both Instruction Level Parallelism (ILP)...
    Resource Type:
    Masters Thesis
    Full Text:
    Simple Scalar tool set was created by Todd Austin. The Simple Scalar architecture is derived from a

  • Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2.5MHz signal bandwidth

    Creator:
    Li, Zhimin
    Abstract:
    In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications. So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s)....
    Resource Type:
    Dissertation
    Full Text:
    and Computer Engineering presented on January 27, 2006. Title: Design of a 14-bit Continuous-Time

  • A VHDL description of speech recognition front-end

    Creator:
    Xiao, Xin
    Abstract:
    This thesis investigates an implementation of speech recognition front-end. It is an application specific integrated circuit (ASIC) solution. A Mel Cepstrum algorithm is implemented for the feature extraction. We present a new mixed split-radix and radix-2 Fast Fourier Transform (FFT) algorithm, which can effectively minimize the number of complex multiplications...
    Resource Type:
    Masters Thesis
    Full Text:
    of Science in Electrical & Computer Engineering presented on May 17, 2001. Title: A VHDL

  • The analysis and synthesis of a parallel sorting engine

    Creator:
    Ahn, Byoungchul
    Abstract:
    This thesis is concerned with the development of a unique parallel sort-merge system suitable for implementation in VLSI. Two new sorting subsystems, a high performance VLSI sorter and a four-way merger, were also realized during the development process. In addition, the analysis of several existing parallel sorting architectures and algorithms...
    Resource Type:
    Dissertation
    Full Text:
    , respectively. Earlier a number of sorting algorithms for other technologies were proposed by Chen and Todd in

  • bBlocks : a flexible object oriented microarchitecture simulation framework

    Creator:
    Hua, Ying
    Abstract:
    This research develops an object-oriented approach of modeling microprocessor architecture. A generic modeling library, bBlocks, is proposed as a framework for constructing microprocessor simulation. bBlocks is a collection of predefined abstract components (blocks) implemented in Java, the object-oriented programming language. Blocks are defined and used as the basic components in...
    Resource Type:
    Masters Thesis
    Full Text:
    of Science in Electrical and Computer Engineering presented on June 19. 2000. Title: bBlocks: A

  • The architecture and design of a parallel sorting engine

    Creator:
    Bate, John G.
    Abstract:
    Sorting is typically a compute intensive operation used in many areas of industry. With improved technology, both in the VLSI and CAE areas, we can afford to develop hardware based database computers to move the work load off the main computer. In this thesis the architecture of a VLSI parallel...
    Resource Type:
    Masters Thesis
    Full Text:
    The architecture and design of a parallel sorting engine