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  • A substrate noise coupling model for lightly doped CMOS processes

    Creator:
    Sadate, Aline C.
    Abstract:
    This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
    Resource Type:
    Masters Thesis
    Full Text:
    used to predict noise coupling between an inverter and an amplifier, with both circuit simulations and

  • Computationally efficient substrate noise coupling estimation in lightly doped silicon substrates

    Creator:
    Srinivasan, Kavitha
    Abstract:
    A Z-parameter based macromodel for characterizing the substrate noise coupling in a lightly doped substrate at low frequencies has been developed. The model is scalable with contact geometries and separation. The cross-coupling impedance between two contacts is modeled using an improved geometric mean distance formulation. This approach obviates the need...
    Resource Type:
    Masters Thesis
    Full Text:
    Figure 1.1. Substrate noise coupling from a digital circuit to an analog circuit

  • Noise optimization for low-voltage CMOS audio preamplifier systems

    Creator:
    Brown, Matthew Eugene
    Abstract:
    There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of...
    Resource Type:
    Masters Thesis
    Full Text:
    this document which will focus on the noise inherent in the circuit devices. 4.2. Zipper Noise

  • A test fixture and deembedding procedure for high-frequency substrate characterization

    Creator:
    Webb, Kyle M.
    Abstract:
    At frequencies exceeding 1-2 GHz, the substrate network models used in substrate coupling simulation must account for the reactive nature of the substrate. Unlike at low frequencies, where the purely resistive substrate models can be validated through DC resistance measurements, these high-frequency models, comprising reactive components, must be validated through...
    Resource Type:
    Masters Thesis
    Full Text:
    market for portable electronic devices, such as cell phones, PDAs, and digital music players, comes a

  • An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

    Creator:
    Arunachalam, Sasi Kumar S.
    Abstract:
    This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
    Resource Type:
    Masters Thesis
    Full Text:
    : An Efficient and Accurate Method of Estimating Substrate Noise Coupling in Heavily Doped Substrates

  • Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

    Creator:
    Hanken, Christopher
    Abstract:
    Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
    Resource Type:
    Masters Thesis
    Full Text:
    alignment is required for correct timing of substrate noise injections from the different circuit blocks

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor

  • A stochastic time-to-digital converter for digital phase-locked loops

    Creator:
    Ok, Kerem
    Abstract:
    Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
    Resource Type:
    Masters Thesis
    Full Text:
    noise performance. This work describes the design and simulation of a stochastic time-to-digital

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    . These include easy scalability with process shrink, elimination of the noise susceptible analog control

  • An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

    Creator:
    Özis, Hatice Dicle
    Abstract:
    A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for...
    Resource Type:
    Masters Thesis
    Full Text:
    designers to simulate the effects of substrate noise in a circuit during the design phase. The model was