This thesis presents a novel methodology that enables power efficient video decoding
in an embedded system based on MPSoC (Multiprocessor System on Chip). This
methodology is a physical combination of parallel processing which reduces power
consumption of processors by exploiting thread-level parallelism and Dynamic
Voltage Frequency Scaling (DVFS) that allows...
The purpose of this thesis is to explore the design of a multimedia extension Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a prototype configurable processor simulator developed at Oregon State University by John Mark...
The purpose of this thesis is to explore dependency speculation in Dynamic Simultaneous Multi-Threading (DSMT). DSMT is a microprocessor architecture which attempts to extract Thread Level Parallelism (TLP) from single-threaded programs at run-time. This is accomplished by running multiple iterations of program loops in parallel. The DSMT architecture was originally...
General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
Within the U.S. there is a growing interest in the case of female adolescents being coerced into the sex industry (Bernstein, 2010; Estes & Weiner, 2001; Soderlund, 2010; Williams and Frederick, 2009). This interest, which emerged due to U.S. involvement in the international trafficking phenomena and grassroots organizing, has resulted...
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Janet Lee
Within the U.S. there is a growing interest in the case of female adolescents
The amount of instruction level parallelism (ILP) that can be exploited depends
greatly on the size of the instruction window and the number of in-flight instructions
the processor can support. However, this requires a register file with a large set of
physical registers for renaming and multiple ports to provide...
The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
This thesis examines the characterization of the femme fatale and the implications of this trope for late-Victorian gender and sexuality in the ghost stories of female aesthete Vernon Lee. In her treatment of the femme fatale figure, Lee both reinforces and complicates the image of the sexualized, often bestialized woman...
Traditional approaches to streaming H.264 video over a network typically rely on a single method of transport (i.e., reliable or unreliable) and/or use static values for parameters that can have a significant negative impact on the perceptual quality of the received video. This dissertation presents a dynamic method for wireless...
Dynamic multithreaded processors attempt to increase the performance of a single
sequential program by dynamically extracting threads from sources such as loop
iterations. The scheduling of instructions in such a processor plays a vital role in the
amount of thread level parallelism that can be extracted and thus the overall...