The objective of this thesis is to describe the design and
implementation of a VSLI reduced instruction set computer (RISC).
The RISC machine constitutes a new style of computer architecture.
It differs significantly from the complex instruction set computer
architectures (CISC) of the past. RISC architectures are
characterized by their...
This paper discusses the design strategies for interface of bus
architectures. It also describes the design of interface between the
two popular bus architectures, the Micro Channel and the Nu Bus.
The main objective of this thesis is to develop a procedure for
bus interface design and use this procedure...
This thesis describes the design of a Reduced Instruction Set Computer. Its instruction memory utilizes a unique cache architecture and a two-stage memory pipelining technique. Because of the bandwidth of the 64-bit instruction bus, instruction prefetching is possible and is implemented. The data memory is bridged by a four-way set-associative...
Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays are synthesized by finding timing and allocation functions which transform index points in the recurrences into points in a space-time domain. The problem of scheduling...
This thesis describes the design of a RISC architecture
for high speed data acquisition. The structure of existing
data acquisition systems is first examined. An instruction
set is created to allow the data acquisition system to serve
a wide variety of applications. The architecture is designed
to allow the execution...
We consider the parallelization of Monte Carlo algorithms for analyzing numerical models of charge transport used in semiconductor device physics. Parallel algorithms for the standard k-space Monte Carlo simulation of a three band model of bulk GaAs on hypercube multicomputers are first presented. This Monte Carlo model includes scattering due...
There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing of programs so as to specify all the available parallelism. The success rate of any of the known techniques is rather poor over all types...
There seems to be a consensus that future Massively Parallel Architectures
will consist of a number nodes, or processors, interconnected by high-speed network.
Using a von Neumann style of processing within the node of a multiprocessor system
has its performance limited by the constraints imposed by the control-flow execution
model....
The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture with only local communication and control and a simple regular structure will result in increased performance. This thesis attempts to analyze the performance of the...