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  • Enabling metal-fill-aware design of integrated circuits

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    In advanced integrated circuit (IC) processes, the metal fill inserted to meet foundry imposed density requirements degrades the performance of interconnects and passive components which ultimately affects the overall circuit performance. Accounting for this degradation through electromagnetic and equivalent circuit modeling is becoming a critical aspect of IC design. However,...
    Resource Type:
    Dissertation
    Full Text:
    availability of computationally efficient models for component design. As the accurate estimation of passive

  • Embedded passives in a multilayer medium

    Creator:
    Seo, Yongseok, 1958-
    Abstract:
    Recent advances in high density low cost RF and microwave three dimensional integration technologies using LTCC(Low Temperature Cofired Ceramics), laminate and other multilayer hybrid and integrated circuits have increased interest in the design of embedded passive components such as inductors, capacitors and filters. The purpose of this study is to...
    Resource Type:
    Dissertation
    Full Text:
    interest in the design of embedded passive components such as inductors, capacitors and filters. The

  • Low noise FSCL digital circuits for decimation filter

    Creator:
    Wong, Man Wa
    Abstract:
    A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
    Resource Type:
    Masters Thesis
    Full Text:
    filter 42 LIST OF TABLES Table Page 1 Comparison of a 4-bit CLA and 4-bit CSA 16 2 Design

  • Switched-current logic for digital circuit design

    Creator:
    Subramanian, Vivek
    Resource Type:
    Masters Thesis
    Full Text:
    . Hodges and G.H. Jackson, Analysis and Design of Digital Integrated Circuits, Mc Graw Hill, 1988. 46

  • Device characterization and analog circuit design for heterojunction FETs

    Creator:
    Wang, Binan
    Abstract:
    Present day data processing technology requires very high speed signal processing and data conversion rates. Traditionally, these circuits have been implemented in silicon MOS technology, whose high speed performance is limited, due to inherent material properties. Though relatively immature compared to silicon technology, GaAs integrated circuit technology appears to be...
    Resource Type:
    Masters Thesis
    Full Text:
    Device Characterization and Analog Circuit Design for

  • A numerical study of the thermal performance for surface mounted and through-hole mounted integrated circuits

    Creator:
    Wang, Jyi-Ren
    Resource Type:
    Masters Thesis
    Full Text:
    Mounted and Through-Hole Mounted Integrated Circuits. AN ABSTRACT OF THE THESIS OF Jyi-Ren Wang for the

  • Substrate coupling macromodel for lightly doped CMOS processes

    Creator:
    Koteeswaran, Mohanalakshmi
    Abstract:
    A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
    Resource Type:
    Masters Thesis
    Full Text:
    sensitive analog and RF circuits. The nOise coupling can be eliminated by improved circuit design [1, 2

  • Zinc tin oxide thin-film transistor circuits

    Creator:
    Heineck, Daniel Philip
    Abstract:
    The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.8 Integrated circuit E-mode TFT log(ID)-VGS transfer curves and mobility plots . . . 70 5.9 ID