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Filtering by: Creator Kim, Ok-Hee Remove constraint Creator: Kim, Ok-Hee Subject Phase-locked loops Remove constraint Subject: Phase-locked loops

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  • Design techniques for high-performance digital PLLs and CDRs

    Creator:
    Yin, Wenjing
    Abstract:
    Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged...
    Resource Type:
    Dissertation

  • Low noise clocking for high speed serial links

    Creator:
    Brownlee, Merrick
    Abstract:
    As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be- come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are...
    Resource Type:
    Dissertation
    Full Text:
    , Min-Gyu Kim, Charlie Myers, Vova Kratyuk, Ting Wu, Jose Ceballos, Martin Vandepas, Kerem Ok, Dong

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    friendship of Dr. Merrick Brownlee, Dr. Volodymyr Kratyuk, Dr. Min-Gyu Kim, Dr. Youn-Jae Kook, Dr. Gil-Cho

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    various circuit design problems. Also I would like to thank MinGyu Kim, Gil-Cho Ahn, Jose Silva, Jose

  • Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

    Creator:
    Young, Brian LeRoy
    Abstract:
    In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback...
    Resource Type:
    Dissertation