The objective of this thesis is to design a high speed digital FIR filter. The inputs of the
system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs,
multiplies them with their coefficients and adds the results. The main design task is to
take the input data, which...
A variable gain, high linearity, low power baseband filter for WLAN applications is implemented in a 1.5 V 3 V 0.15 μm CMOS process. This fourth-order low-pass filter, which is introduced in the transmit channel as a reconstruction filter between the D/A converter and the mixer, has a measured cut-off...
Mobile and telecommunication industry has experienced tremendous growth in the recent past. Miniaturization and increased functionality have become necessary for all passive components in the system. Bandpass filters are critical passive components in any communication system and the existing designs in the crucial 1-10 GHz bandwidth suffer many drawbacks. For...
A new approach to oversampled delta-sigma A/D converters ( AZ modulators ) is introduced, where a differential pseudo-Npath filter stage is used as a basic cell. In this band-pass application, the z to -zN transformation is employed to realize a RAM-type pseudo-2-path lossless integrator. The bandpass second-order and 4th-order delta-sigma...
The design and implementation of Switched-Current (SI) ladder filters is
described. SI filters require only a standard digital CMOS process and the power
supply voltage requirement is low. SI circuits also can be potentially operated at
higher frequencies than Switched-Capacitor (SC) filters due to the low-impedance
wideband nodes of the...
Clock-feedthrough effects, channel-length modulation and device mismatch are
the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these
non-ideal effects are analyzed. A high-performance current mirror, namely regulated
cascode current mirror, which eliminates drain voltage variation problem is introduced.
By using this current mirror as a...
A new structure for the implementation of bit/serial adaptive IIR filter is
presented. The bit level system consists of gated full adders for the arithmetic
unit and data latches for the data path. This approach allows recursive
operation of the IIR filter to be implemented without any global
interconnections, minimal...
Pulse Width Modulation (PWM) has been used extensively for motor control, DC-AC
converters, DC-DC converters and in audio applications. The conventional method of
generating a pulse width modulated signal involves generating an accurate sawtooth or triangle
wave using analog circuits. In CMOS, being analog circuit intensive puts extra constraints
on...
Direct-conversion architecture would dominate the modern low power wireless receiver architecture if problems such as offset cancellation, even-order distortion, and flicker noise were solved. Among those problems, offset is the most serious one. This thesis will discuss and analyze one approach to cancel offsets in direct-conversion receivers. First, we explain...
The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has...