Index Catalog // ScholarsArchive@OSU

Start Over

Filtering by: Subject Decoders (Electronics) -- Energy consumption

Power efficient H.264 video decoding in embedded multiprocessor

Creator:

Kim, Jihong

Abstract:

This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...

Resource Type:

Masters Thesis

Full Text:

............................................. 44 27. Total energy consumption by proposed method
Simulator for optimizing performance and power of embedded multicore processors

Creator:

Goska, Benjamin J.

Abstract:

This work presents improvements to a multi-core performance/power simulator. The improvements which include updated power models, voltage scaling aware models, and an application specific benchmark, are done to increase the accuracy of power models under voltage and frequency scaling. Improvements to the simulator enable more accurate design space exploration for...

Resource Type:

Masters Thesis

Full Text:

used to calculate power consumption, then energy was calculated by: E = P · T . 4.2.1 Core Model For
Low-power high-resolution delta-sigma ADC design techniques

Creator:

Wang, Tao

Abstract:

This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the...

Resource Type:

Dissertation

Full Text:

] N.Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rate-resolution scalable SAR ADC for