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Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells

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Abstract
  • It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the piecewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9dB (without calibration) is achieved at 210MSPS from the Verilog synthesized design.
  • This is an author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919]. ©201X IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
  • Keywords: Circuit synthesis, Analog-digital conversion, Stochastic systems
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  • Weaver, S., Hershberg, B., & Moon, U. (2014). Digitally synthesized stochastic flash ADC using only standard digital cells. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(1), 84-91. doi:10.1109/TCSI.2013.2268571
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  • 61
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  • 1
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  • This work was supported by the Semiconductor Research Corporation (SRC), and the Center for Design Analog-Digital Integrated Circuits (CDADIC).
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