Graduate Thesis Or Dissertation

Investigating Time-Digital-Converters for Hardware Security in FPGAs

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  • In this comprehensive thesis, we present a series of experiments and findings that highlight the critical importance of TDC Voltage Sensors in the hardware security domain. Our research begins by introducing a novel self-calibrating module, demonstrating its efficiency through preliminary calibration tests. We then delve into the Peak-to-Peak tests, which underscore the significance of calibration in achieving optimal quantization levels for glitch detection, while also discussing the trade-offs between delay line lengths. We investigate two types of power consumption devices, RO and SC arrays, revealing their distinct advantages and the need for designers to carefully consider their implementation based on specific requirements. Moving forward, we explore the mapping of TDC Voltage sensors and the effectiveness of power consumption modules across various positions on a circuit board, emphasizing their adaptability and potential threat of using them by malicious actors. Furthermore, our noise test showcases the potential exploitation of SC arrays in fault injection attacks, drawing attention to the need for countermeasures to prevent their misuse. Additionally, we highlight the protective potential of power consumption modules in obscuring sensitive side-channel information. In summary, our research underscores the critical role of TDC delay line-based sensors, calibration techniques, and power consumption arrays in hardware security. These findings advocate for their strategic incorporation into hardware architecture as a preemptive measure against potential design vulnerabilities, ultimately contributing to the advancement of robust hardware security solutions.
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