Silencer! : a tool for substrate noise coupling analysis

Graduate Thesis Or Dissertation

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Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/g158bm41v

Descriptions

Attribute Name	Values
Creator	Birrer, Patrick
Abstract	This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different levels of hierarchy - from a level where only an approximate layout of the transistors is known to a level that incorporates various parasitic elements. It can be used for layout optimization to reduce substrate cross-talk noise between circuitry that injects noise into the substrate and other circuitry that is sensitive to it. Examples in a TSMC 0.35μm heavily doped process have been simulated and the results are in good agreement with measured fabricated chips.
License	All rights reserved
Resource Type	Masters Thesis
Date Available	2009-05-27T21:31:34+00:00
Date Issued	2003-01-09
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	2004
Advisor	Fiez, Terri S. Mayaram, Kartikeya
Academic Affiliation	Electrical Engineering and Computer Science
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Substrate noise Mixed signal circuits -- Noise
Urheberrechts-Erklärung	In Copyright
Publisher	Oregon State University
Language	English [eng]
Replaces	http://hdl.handle.net/1957/11735

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