A DAC and comparator for a 100MHz decision feedback equalization loop Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/g732dc83n

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  • Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW.
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