Graduate Thesis Or Dissertation
 

Interlaced instruction window

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/pg15bh254

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  • A relatively recent development in the late 1980s in processors has been the superscalar processor. Superscalar processors use multiple pipelines in an attempt to achieve higher performance than previous generations of processors. Having multiple pipelines makes it possible to execute more than one instruction per cycle. However, since instructions are not independent of one another, but are interdependent, there is no guarantee that any given sequence of instruction will take advantage of the wider pipeline. One major factor that governs the ability of a processor to discover parallel instructions is the processor's mechanism for decoding and executing instruction. For superscalar processors with the central window design, the number of parallel instructions discovered is dependent on the size of the window. With a large window, the probability that the processor can find more parallel instructions is higher because there are more instruction to choose from. However, the larger the window the longer the critical path and thus lower clock speed. The major theme of this thesis is to find ways to have a large instruction window but still have clock speed comparable to a small instruction window processor. One way to achieve this is to apply the idea of memory interleaving to the processor's instruction window or reservation station design. With interleaving, there are multiple small instruction windows instead of one large window. In the first cycle the first window is used, and the second window is used in the second clock cycle. After all windows are used, the processor returns to the first window. Therefore with the interleaved design only a small portion of the whole instruction window is active at one time. In this way, there can be a large virtual window. Furthermore since the size of individual window is kept small, the clock speed is not affected. The rest of this thesis will explain how this interleaved instruction window scheme works and also list some simulation results to show its performance.
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