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Filtering by: Creator Johnsen, S. J. Remove constraint Creator: Johnsen, S. J. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya

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  • A nano-power wake-up circuit for RF energy harvesting wireless sensor networks

    Creator:
    Lindsley, Christopher J.
    Abstract:
    A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 36nA static current at 20°C and dissipates 2pJ of energy per conversion. The comparator comprises of...
    Resource Type:
    Masters Thesis
    Full Text:
    J. Lindsley for the degree of Master of Science in Electrical and Computer Engineering presented

  • Low power receivers for wireless sensor networks

    Creator:
    Ni, Ronghua
    Abstract:
    Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the battery life of the nodes. In this dissertation, two low power BFSK receiver architectures are proposed and verified with prototype implementations in silicion. A 2.4...
    Resource Type:
    Dissertation
    Full Text:
    Networks Abstract approved: Terri S. Fiez Kartikeya Mayaram Wireless sensor networks are becoming

  • Ultra-low-energy transmitters for battery-free wireless sensor networks

    Creator:
    Panitantum, Napong
    Abstract:
    As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an ultra-low-energy WSN transmitter is developed to reduce the energy consumption of sensor nodes in WSNs. With an ultra-low-energy transceiver, it is possible to eliminate the...
    Resource Type:
    Dissertation
    Full Text:
    . Abstract approved: ____________________________________________________________________ Terri S. Fiez

  • A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

    Creator:
    Hazenboom, Duncan S.
    Abstract:
    Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Duncan S. Hazenboom for the

  • Ultra-low power receivers for wireless sensor networks

    Creator:
    Ayers, James S.
    Abstract:
    In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed. A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show...
    Resource Type:
    Dissertation
    Full Text:
    AN ABSTRACT OF THE DISSERTATION OF James S. Ayers for the degree

  • An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

    Creator:
    Arunachalam, Sasi Kumar S.
    Abstract:
    This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Sasi Kumar S. Arunachalam for the

  • A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

    Creator:
    Ayers, James S.
    Abstract:
    An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF James S. Ayers for the degree of

  • Development and Implementation of JetNet : A Decentralized Wireless Sensing Protocol

    Creator:
    Goins, Justin B.
    Abstract:
    Modern sensor network applications are often implemented wirelessly in order to lessen installation costs and reduce deployment times. Unfortunately, these wireless sensor network (WSN) nodes must often rely on batteries or energy harvesting techniques in order to sustain their operation and supply the power needed to maintain communication within the...
    Resource Type:
    Dissertation
    Full Text:
    : Kartikeya Mayaram Terri S. Fiez Modern sensor network applications are often implemented wirelessly in

  • An ultra low power frequency reference for timekeeping applications

    Creator:
    Oporta, Hector Ivan
    Abstract:
    An ultra low power crystal oscillator that provides a frequency reference for battery powered timekeeping applications is presented. An amplitude control circuit is employed to ensure that minimum current is consumed. A subthreshold voltage regulator provides a supply voltage for the oscillator with minimum current consumption. The oscillator and regulator...
    Resource Type:
    Masters Thesis
    Full Text:
    Ultra Low Power Frequency Reference For Timekeeping Applications Abstract approved: Terri S. Fiez

  • Noise and Blocker Cancellation Techniques for Power and Area Efficient Wireless Receivers

    Creator:
    Pourbagheri, Saeed
    Abstract:
    The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique...
    Resource Type:
    Dissertation
    Full Text:
    Kartikeya Mayaram Terri S. Fiez The design of mobile wireless devices has always

  • Power Efficient Hybrid Architecture for High Resolution Analog-to-Digital Converters

    Creator:
    Zhang, Hui
    Abstract:
    Analog-to-digital converters (ADCs) are the key building block for sensor applications, such as wireless communications and digital electronics. These applications require ADCs to have medium to high accuracy (normally from 10-14 bits) and relatively low signal bandwidth (ranging from 100Hz-150kHz). Since these applications are often powered by batteries, high power...
    Resource Type:
    Masters Thesis
    Full Text:
    . 530-535. [2] J. Hayes, S. Beirne, L. King-Tong, and D. Diamond, “Evaluation of a low-cost wireless

  • Ultra-low energy digital controller for battery-free wireless sensor network nodes

    Creator:
    Nasroullahi, Mohsen
    Abstract:
    This thesis presents a low-energy application specific digital controller for a battery-free 2.4 GHz wireless sensor network (WSN) node. The digital controller has been designed and fabricated in a standard 0.13 μm CMOS and implements a simple protocol for WSNs. Techniques such as supply voltage reduction and power gating have...
    Resource Type:
    Masters Thesis
    Full Text:
    : Terri S. Fiez Kartikeya Mayaram This thesis presents a low-energy application specific digital

  • An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

    Creator:
    Farahbakhshian, Farhad
    Abstract:
    An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
    Resource Type:
    Masters Thesis
    Full Text:
    –329, May. 2005. [19] S. J. Yun, S. B. Shin, H. C. Choi, and S. G. Lee, “A 1mW current-reuse CMOS

  • A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs

    Creator:
    Miller, Brian A.
    Abstract:
    This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics. The chip has been fabricated in a 130nm CMOS technology. To meet the power demands of body powered networks, a novel dual-path architecture capable of...
    Resource Type:
    Masters Thesis
    Full Text:
    Thermoelectric Generators for use in Body-Powered Designs Abstract approved: Terri S. Fiez

  • Ultra-low energy digital logic controller design for wireless sensor networks

    Creator:
    Meliza, Stephen W.
    Abstract:
    Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital...
    Resource Type:
    Masters Thesis
    Full Text:
    Energy Digital Logic Controller Design for Wireless Sensor Networks Abstract approved: Terri S. Fiez

  • Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

    Creator:
    Hsu, Shu-ching
    Abstract:
    This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Kartikeya Mayaram Tern S. Fiez This thesis examines substrate noise coupling for NMOS

  • Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

    Creator:
    Sharma, Ajit
    Abstract:
    This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Kartikeya Mayaram Tern S. Fiez This thesis presents an automated methodology to calibrate the

  • A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

    Creator:
    Held, Martin A.
    Abstract:
    A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
    Resource Type:
    Masters Thesis
    Full Text:
    Large Scale Digital Circuits in Mixed Signal SoC's Abstract approved: 4 a Terri S. Fiez Kartikeya

  • Silencer! : a tool for substrate noise coupling analysis

    Creator:
    Birrer, Patrick
    Abstract:
    This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
    Resource Type:
    Masters Thesis
    Full Text:
    . Abstract approved: Kartikeya Mayaram Terri S. Fiez This thesis presents Silencer!, a

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    Substrate Noise Due to Clocked and Clockless Circuitry Abstract approved: Terri S. Fiez Kartikeya Mayaram

  • Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

    Creator:
    Hanken, Christopher
    Abstract:
    Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
    Resource Type:
    Masters Thesis
    Full Text:
    Circuits Abstract approved: Terri S. Fiez Karti Mayaram Efficient methods for simulating the substrate

  • Steady-state analysis techniques for coupled device and circuit simulation

    Creator:
    Hu, Yutao
    Abstract:
    The focus of this work is on the steady-state analysis of RE circuits using a coupled device and circuit simulator. Efficient coupling algorithms for both the time-domain shooting method and the frequency-domain harmonic balance method have been developed. A modified Newton shooting method considerably improves the efficiency and reliability of...
    Resource Type:
    Dissertation
    Full Text:
    . I would like to thank Dr. Solomon C. S. Yim, Dr. Tern Fiez, Dr. Un-Ku Moon, and Dr. Raghu Settaluri

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    gain GC(s) is domi- nant at frequencies below ωe, and the fine loop gain GF (s) is domi- nant at

  • A test fixture and deembedding procedure for high-frequency substrate characterization

    Creator:
    Webb, Kyle M.
    Abstract:
    At frequencies exceeding 1-2 GHz, the substrate network models used in substrate coupling simulation must account for the reactive nature of the substrate. Unlike at low frequencies, where the purely resistive substrate models can be validated through DC resistance measurements, these high-frequency models, comprising reactive components, must be validated through...
    Resource Type:
    Masters Thesis
    Full Text:
    ) second deembedding steps. 39 5.3 Simulated S-parameters for a 1 KΩ resistor embedded in the test fixture

  • Analysis and Design of Low Voltage LC Oscillators and their Application to Wireless Sensor Networks

    Creator:
    Guha Roy, Ankur
    Abstract:
    This dissertation focuses on the analysis, design, and application of inductor-capacitor (LC) oscillators for wireless sensor networks (WSNs). First an analysis and design optimization approach for enhanced swing, low power CMOS LC oscillators is presented. A phasor based analysis is used for determining the amplitude and phase noise of these...
    Resource Type:
    Dissertation
    Full Text:
    t approved: Kartikeya Mayaram Terri S. FiezThis dissertation fo uses on the analysis, design, and

  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 s-domain model for a second-order DPLL . . . . . . . . . . . . . . . . . 10 2.3.2 Design

  • Frequency domain steady-state simulation of oscillators

    Creator:
    Duan, Xiaochun
    Abstract:
    The focus of this work is on developing algorithms for frequency domain steady-state analysis of oscillators. Convergence problems associated with the frequency domain harmonic balance simulation of oscillators have been examined. Globally convergent homotopy methods have been combined with the harmonic balance method for robust high-Q oscillator simulation. Various homotopy...
    Resource Type:
    Dissertation
    Full Text:
    series: t)(�Xt)(�XXx(t) i s i i i c i sincos 1 0 ++= � ∞ = (2.1) where iω is the frequency

  • Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs

    Creator:
    Sundaresan, Arathi
    Abstract:
    The substrate noise injected by a stepped buffer circuit into two single-ended 1.5GHz low noise amplifiers is examined for a heavily doped 0.25µm CMOS process. The difference in the LNA noise rejection is characterized as a function of the size and placement of substrate contacts. The use of a resistive...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: _____________________________________________________________ Terri S. Fiez Kartikeya

  • Contributions to substrate noise due to supply coupling and pin parasitics

    Creator:
    Adluri, Sirisha
    Abstract:
    This thesis presents the contributions to substrate noise due to supply coupling and the effect of pin parasitics on the substrate noise generated by digital circuits. Various sources of substrate noise and their effect on analog circuits sharing the same substrate are discussed. A simulation approach to isolate the various...
    Resource Type:
    Masters Thesis
    Full Text:
    ) output, V / % I j ' I I I 'I, II it' } = Schematic showing the Ldi/dt effect of an inductor in

  • A stochastic time-to-digital converter for digital phase-locked loops

    Creator:
    Ok, Kerem
    Abstract:
    Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
    Resource Type:
    Masters Thesis
    Full Text:
    reference period. 29 BIBLIOGRAPHY [1] R. B. Staszewski, J. Wallberg, S. Rezeq, C. Hung, O

  • Modeling and simulation methods for RF MEMS VCOs

    Creator:
    Sankaranarayanan, Janakiram Ganesh
    Abstract:
    This work focusses on the modeling and the development of efficient coupled simulation techniques for MEMS based RF oscillators. High-level models for MEMS based varactors have been discussed and their accuracy issues are identified, based on comparisons with numerical simulations. A faster simulation approach based on the time-domain shooting method...
    Resource Type:
    Masters Thesis
    Full Text:
    domain and the transfer function between the force Fe and the displacement X(s) is given by X(s) Fe(s

  • Substrate noise coupling in ring oscillator-based phase locked loops

    Creator:
    Shreeve, Robert
    Abstract:
    In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
    Resource Type:
    Masters Thesis
    Full Text:
    1200120012001200 1400140014001400 R es is ta n ce ( o h m s) Measurement Calculation

  • Automated analysis, design, and optimization of low noise oscillators

    Creator:
    Vytyaz, Igor
    Abstract:
    Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . 15 2.2 PSS waveforms and their difference in normalized time. The differ- ence ∆τs is small for

  • An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking

    Creator:
    Heiberg, Adam C.
    Abstract:
    A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system operates with a supply voltage down to 250 mV. A prototype has been fabricated in a 0.13μm CMOS process and includes a low voltage LNA, quadrature oscillators, and quadrature mixers. It exhibits...
    Resource Type:
    Masters Thesis
    Full Text:
    S. Fiez Kartikeya Mayaram A fully integrated CMOS GPS receiver RF front end optimized for low power

  • Algorithms and tools for optimization of integrated RF VCOs

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    This thesis presents algorithms and tools for the automated design of RF LC CMOS voltage controlled oscillators (VCOs) with low phase noise given a set of specifications. The electromagnetic solver, ASITIC, combined with the circuit simulator, SpectreRF, allows optimization of the VCO circuit parameters and inductor layout. This approach gives...
    Resource Type:
    Masters Thesis
    Full Text:
    Science Dean of the Graduate S I understand that my thesis will become part of the permanent collection

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    same names used to define their equivalent regions on the circuit layout shown in Figure 2.3. tap S Ml

  • Design techniques for radiation hardened-phase locked loops

    Creator:
    Nemmani, Anantha Nag
    Abstract:
    Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit...
    Resource Type:
    Masters Thesis
    Full Text:
    outputs are converted to a 10-bit 2’s complement signed digital word through the pseudo-thermometer

  • Coupled circuit and device simulations for design of RF MEMS VCOs

    Creator:
    Behera, Manas
    Abstract:
    A new coupled circuit and electrostatic/mechanical simulator (COSMO) for the design of RF MEMS VCOs is presented in this thesis. The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating...
    Resource Type:
    Masters Thesis
    Full Text:
    early 1980s, significant work has been done in the field of coupled simulation. In the late 1980’s

  • Comparison of time-domain and frequency-domain phase noise analyses

    Creator:
    Vytyaz, Igor
    Abstract:
    This thesis presents a comparison of time-domain and frequency-domain algorithms for phase noise calculation in oscillators. Floquet theory provides the mathematical foundation for these calculations and the numerical methods employ perturbation projection vectors (PPVs). The PPVs are an estimate of an oscillator's sensitivity to noise. The in-house circuit simulator SPICE3...
    Resource Type:
    Masters Thesis
    Full Text:
    practice, noise from semiconductor devices, 0 0.25 0.5 0.75 1 0 Time (ns) x s (t) 0 1 2 3 4 Frequency

  • Efficient RF energy scavenging and ultra-low power management for powering wireless sensor nodes

    Creator:
    Arumugam, Vikrant P.
    Abstract:
    As the demand for real-time information in engineering and health care systems keeps increasing, the need for wireless sensor nodes is also continuously increasing. As a result, the cost and effort involved in installing and maintaining batteries to power the numerous sensor nodes is growing exponentially. Providing a cost effective...
    Resource Type:
    Masters Thesis
    Full Text:
    higher 8 ! " #! #" $! $"#! !% #!!& #!!' #!!$ #!! ()s+ance0123 R ec e) ve d0 7o 9 er 01; 3

  • Oscillators and phase locked loops for space radiation environments

    Creator:
    Vandepas, Martin
    Abstract:
    Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic radiation and require special design consideration. The purpose of this work is to explore methods of mitigating the effect of radiation in phase locked loop (PLL) circuits. Several voltage controlled oscillators (VCOs) and two complete PLLs are designed and...
    Resource Type:
    Masters Thesis
    Full Text:
    BIBLIOGRAPHY [1] J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-bias techniques

  • Computationally efficient substrate noise coupling estimation in lightly doped silicon substrates

    Creator:
    Srinivasan, Kavitha
    Abstract:
    A Z-parameter based macromodel for characterizing the substrate noise coupling in a lightly doped substrate at low frequencies has been developed. The model is scalable with contact geometries and separation. The cross-coupling impedance between two contacts is modeled using an improved geometric mean distance formulation. This approach obviates the need...
    Resource Type:
    Masters Thesis
    Full Text:
    Silicon Substrates. Abstract approved: Kartikeya Mayaram Terri S. Fiez A Z