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Filtering by: Creator Kirinicich, A. R. Remove constraint Creator: Kirinicich, A. R. Advisor Temes, Gabor C. Remove constraint Advisor: Temes, Gabor C. Committee Member Nguyen, Thinh Remove constraint Committee Member: Nguyen, Thinh

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  • Low-power successive approximation analog to digital converter with digital calibration

    Creator:
    Li, Wei
    Abstract:
    IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This...
    Resource Type:
    Dissertation
    Full Text:
    . P. U, R. P. Martins, and F. Maloberti, "A 10-bit 100 MS/s reference-free SAR ADC in 90 nm CMOS

  • Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

    Creator:
    Wang, Yan
    Abstract:
    Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations...
    Resource Type:
    Dissertation
    Full Text:
    radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time

  • Power Efficient Architectures for Medium-high Resolution Analog-to-Digital Converters

    Creator:
    Sadollahi, Mahmoud
    Abstract:
    Analog-to-digital converters are essential components to the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth require low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In this work power efficient ADCs for...
    Resource Type:
    Dissertation
    Full Text:
    total power consumption was 250 nW from a 0.75V supply voltage. This gives a Walden FoM of 28.8 fJ

  • Linearity enhancement techniques for data converters

    Creator:
    Cao, Jinzhou
    Abstract:
    Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC)....
    Resource Type:
    Dissertation
    Full Text:
    a tradeoff against other performance criteria, is one of the major performance demands from

  • Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling Rate

    Creator:
    He, Tao
    Abstract:
    Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
    Resource Type:
    Dissertation
    Full Text:
    . However, at multi-GHz clock rates, dynamic errors introduced by inter-symbol interference in a multi-bit

  • Design techniques for low power high speed successive approximation analog-to-digital converters

    Creator:
    Lin, Jiaming
    Abstract:
    This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
    Resource Type:
    Dissertation
    Full Text:
    were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step