Index Catalog // ScholarsArchive@OSU

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Creator:: Shakya, Jyotindra R.
Abstract:: Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color...
Resource Type:: Dissertation

5th-Order Elliptic LPF Using Passive Charge Compensation Technique (PCC) Design

Creator:: Tsai, Cheng H.
Abstract:: The passive charge compensation (PCC) technique was introduced for switched capacitor (SC) circuit to increase the slew rate and enhance the linearity performance, as PCC techniques are used on the Delta-Sigma modulator (DSM) in ADC circuitry. The PCC technique of the project was applied to the design of a SC...
Resource Type:: Masters Thesis

Low-Power 12-bit Quasi-Passive Segmented DAC Implemented in 130nm CMOS Technology

Creator:: Pierce, Alexander G.
Abstract:: This thesis work proposes a low-power 12-bit digital-to-analog converter (DAC) designed in a 130nm process. The DAC to be presented is of a segmented design where the architecture is split into pipelined and thermometer coded segments. This allows for high linearity and low distortion while maintaining high speed and low...
Resource Type:: Masters Thesis

Switched Capacitor Circuit Techniques for High Performance CMOS Analog Circuits

Creator:: Kareppagoudr, Manjunath
Abstract:: Switched capacitor (SC) circuits are the main building blocks in many structures such as filters, data converters, sampling circuits and sampled-data amplifiers. The key challenge is to design such circuits which are the prime components of any IoT system with low power consumption without compromising on the performance. In this...
Resource Type:: Dissertation

A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs

Creator:: Wang, Yanchao
Abstract:: The sensors in real time data processing IoT devices require high resolution and sub-MHz data converters, usually implemented as Incremental ADCs due to the advantages of oversampling technique and low latency. In discrete time incremental (IDT) ADCs, the sampling switch non-linearity, charge injection degrade the resolution, and power hungry OPAMPs...
Resource Type:: Dissertation

Active Noise Shaping Analog-to-Digital Data Converters

Creator:: Shi, Lukang
Abstract:: Successive-approximation-register (SAR) analog-to-digital converters are popular for medium accuracy, medium speed and low power applications, such as in biomedical applications. They have low latency and simple architecture compared with ΔΣ ADCs. This is because of SAR ADCs’ binary searching scheme. Furthermore, SAR ADCs can apply oversampling and noise shaping schemes...
Resource Type:: Dissertation

Power Efficient Architectures for Low Noise Switched-Capacitor Filters and High Accuracy Analog-to-Digital Converters

Creator:: Payandehnia, Pedram
Abstract:: Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-deﬁned radios and internet-of-things. In this dissertation, novel switched-capacitor ﬁlter and analog-to-digital converter (ADC) circuit conﬁgurations have been explored which are power eﬃcient and are digital scaling friendly. First, a novel switched-capacitor low-pass ﬁlter architecture...
Resource Type:: Dissertation

Power Efficient Architectures for Medium-high Resolution Analog-to-Digital Converters

Creator:: Sadollahi, Mahmoud
Abstract:: Analog-to-digital converters are essential components to the portable devices that we are using today. Wireless sensors, body implanted devices, communication devices and so forth require low power ADCs. Therefore achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. In this work power efficient ADCs for...
Resource Type:: Dissertation

Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling Rate

Creator:: He, Tao
Abstract:: Continuous-time ΔΣ modulators are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requirements while maintaining good power efficiency, multi-bit feedback is typically used. This approach provides benefits such as lower OSR, relaxed loop filter requirements, and reduced jitter sensitivity....
Resource Type:: Dissertation

Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

Creator:: Meng, Xin
Abstract:: Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
Resource Type:: Dissertation

ScholarsArchive@OSU

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

5th-Order Elliptic LPF Using Passive Charge Compensation Technique (PCC) Design

Low-Power 12-bit Quasi-Passive Segmented DAC Implemented in 130nm CMOS Technology

Switched Capacitor Circuit Techniques for High Performance CMOS Analog Circuits

A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs

Active Noise Shaping Analog-to-Digital Data Converters

Power Efficient Architectures for Low Noise Switched-Capacitor Filters and High Accuracy Analog-to-Digital Converters

Power Efficient Architectures for Medium-high Resolution Analog-to-Digital Converters

Dynamic Error Calibration for Continuous-Time Delta-Sigma Modulator with Multi-GHz Sampling Rate

Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

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