Low-power receivers (RX) with 100$\mu W$-scale power consumption can enable several power/energy-constrained IoT applications. However, achieving sensitivity, interferer tolerance and wide operating range with low power presents a challenge for existing architectures, particularly those constrained to highly integrated solutions without high-Q off-chip components. Existing solutions rely heavily on high quality...
Modern sensors are complex systems comprising multiple sub-systems such as transducers, analog and mixed-signal interface circuits, digital processing circuits, and packaging. Over the last few decades, innovations in these sub-systems combined with their increased integration in complementary metal-oxide semiconductor (CMOS) processes have led to the rapid growth in sensors for...
Dense electrical recording of biosignals has been developed to provide spatial resolution and precise temporal information for health monitoring, diagnostics, and clinical research. However, more electrodes require more wires, and wiring density quickly becomes a limiting factor. To break this bottleneck, we proposed a frequency-division multiplexing (FDM) based architecture for...
Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency...
The need for sustainably powering unobtrusive internet-of-things applications has led to an interest in energy harvesting. Particularly, the proliferation of wireless communication and devices in the 2.4 GHz Industrial Scientificc Medical (ISM) band creates an opportunity to leverage commonly used devices for RF powering. This dissertation presents a low-quiescent-power...
Ever increasing global internet data traffic has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals suffering from greater channel loss and exponential increase...
Over the last decades, CMOS-integrated sensors have made impressive progress in performance, form-factor, and energy-efficiency for various applications such as imaging, physical/chemical sensing, bio/health monitoring. In the era of the artificial intelligence (AI) and the internet-of-things (IoT), such CMOS-integrated sensors are essential for massive and comprehensive data acquisition, where sensing...
Conventional Delta-Sigma analog-to-digital converters (ADCs) utilize operational transconductance amplifiers (OTAs) in their loop filter implementation followed by multi-bit voltage domain quantizers. As CMOS integrated circuit technology scales to smaller geometries, the minimum transistor length and the intrinsic gain of the transistors decrease. Moreover, with process scaling the voltage headroom decreases...
In any biomedical signal acquisition system, a front-end amplifier is needed to amplify low amplitude bio-signals while filtering out any unwanted low-frequency artifacts. The design of low frequency poles within the sub-Hz range implies very large time-constants which goes against system integrability. In recent years, the pseudo resistor has been...
Filters and data converters are key analog-and-mixed-signal (AMS) building blocks in communication systems, such as software-defined radios and internet-of-things. In this dissertation, novel switched-capacitor filter and analog-to-digital converter (ADC) circuit configurations have been explored which are power efficient and are digital scaling friendly.
First, a novel switched-capacitor low-pass filter architecture...
The prevalence of Internet-of-Things (IoT) applications leads to an increasing focus on the design and optimization of sensor nodes. Battery lifetime and associated costs of battery replacement often limits the long term operation and viability of sensor nodes. RF wireless energy harvesting on the other hand can be appealing since...
Scalable array transceivers with wide frequency tuning range are attractive for next-generationradios. Key challenges for such radios include generation of LO signals with widefrequency tuning range, scalable synchronization between multiple array unit cells andtolerance to in-band and out-of-band interferers. This thesis presents approaches toaddress these challenges in commercial CMOS technologies.The...
This work presents a new data encoding scheme: Integrated Pulse Width Modulation (iPWM) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed scheme is able to overcome the fundamental limitations imposed by Manchester and Pulse Width Modulation (PWM) encoding on high data rate...
The rapid scaling of network bandwidth and data center throughput has motivated the wide adoption of high speed transceivers. Silicon photonics (Si-Photonic) is one of the most promising techniques to realize tightly integrated optical transceivers for next-generation high speed I O standards. This dissertation focuses on the design techniques of...
This work presents the design and implementation of a low power phased-array receiver frontend at 28 GHz in 65 nm CMOS. The frontend incorporates a low- power low-noise amplifier(LNA) and a passive reflection-type phase shifter (RTPS) capable of providing 360° phase shift with 5-bit phase resolution and low loss variation....
All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to address a range of applications and low phase noise requirements. In this thesis, novel resonator structures with ne capacitance/inductance switching...
Nowadays, needs for wideband and high accuracy analog-to-digital converter are increasing rapidly in manifold applications such as wireless communication, digital video and other consumer electronics. Besides, low power consumption is required to have longer battery life in portable systems. CMOS technology scaling and innovative modulator topology make the implementation much...
Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately, the relationship between low-voltage operation and radiation-induced soft error rate is not widely known, as little research has been previously performed and reported for soft-error...
As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links...
The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in...
VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are...
Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design of digital sensor readout circuits quite challenging. Traditionally, these circuits are realized using amplifiers with passive feedback or precision analog comparators which are power hungry...
Incremental ADCs (IADCs) have many advantages for low-frequency high-accuracy data conversion—they are easy to multiplex between channels, need simpler digital decimation filter, and allow extended counting with a Nyquist-rate ADC. A single-loop incremental ADC was designed and fabricated in 90 nm for a biosensor interface circuit. It incorporates one integrator,...
This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively.
The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback...
Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based ADCs behave like an open-loop continuous time ΔΣ modulator and achieve excellent resolution by first order noise shaping the quantization error. However, the SNDR of...
Delta-sigma modulators are currently a very popular technique for making high-resolution
analog-to-digital and digital-to-analog converters (ADCs and DACs). Most
delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback,
the use of multi-bit...
It has been verified by theoretical analysis, circuit simulation and test that two
switch transistors in parallel in a simple sample and hold circuit can be achieve high speed
with low error voltage due to charge injection. The wide transistor provides low RC time
constant when it is closed and...
Delta-sigma modulators are currently a very popular technique for making high-resolution
analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
These oversampled data converters have several advantages over conventional Nyquist-rate
converters, including an insensitivity to many analog component imperfections, a
simpler antialiasing filter and reduced accuracy requirements in the sample and hold....
In recent years, there has been an extensive effort to develop low-cost implementations
of radio frequency integrated circuits for consumer applications. This thesis is a
research effort in the design and implementation of integrated RF CMOS Power Amplifiers
(PAs). A significant challenge in the implementation of RF CMOS ICs is...
This thesis describes compensation techniques for cascaded delta-sigma A/D
converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various
correlated-double-sampling (CDS) techniques are presented to reduce the effects of the
nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and
offset, and finite opamp gain, in SC circuits. A CDS technique...
As the performance gap between processor and memory grows, memory latency will be a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question however remains as to how effective...
The precise measurement of a capacitance difference or ratio in a digital form is
very important for capacitive sensors, for CMOS process characterization as well as for the
realization of precise switched-capacitor data converters, amplifiers and other circuits
utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor
ratio...
The application of information theory and digital signal processing techniques to digital
communication has resulted in robust methods for reliable high speed data transmission
over noisy channels environments. Among these methods, multicarrier systems have
become a viable solution for exploiting maximum spectral efficiency over both wideband
highly dispersive static and...
The thesis presents a new algorithm and structure that is to be used in conjunction with a specially modified CMOS Gilbert cell mixer to remove time-varying DC offsets in direct conversion receivers. In our approach, the DC offset is detected at the output of the mixer using a dedicated coarse...
In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order...
Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate...
The transition from second-generation (2G) to third-generation (3G) wireless cellular and cordless telephone systems requires multi-standard adaptability in a single RF receiver equipment. An important answer to this request is the use of Delta-Sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic range requirements for digital signal processing, and...
Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on eliminating the issues associated with the state of the art switching converters by proposing three novel control techniques: (1) a digitally controlled Buck-Boost converter uses...
The focus of this work is on the steady-state analysis of RE circuits using a coupled device and circuit simulator. Efficient coupling algorithms for both the time-domain shooting method and the frequency-domain harmonic balance method have been developed. A modified Newton shooting method considerably improves the efficiency and reliability of...
In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart
from being capable of handling a wide range of data rates, the transceivers should
have low power consumption (mW/Gbps) and be fully integrated. This work
discusses enabling techniques...
As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but...
Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs...
Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling...
As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues include smaller transistor intrinsic gains and lower supply voltages. However, scaling continues to increase the speed and decrease the power of digital circuits. In this...
Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged...
High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and...
Modern day digital systems employ frequency
synthesizers to provide a common clock to the system.
They are undergoing large scale integration due to which, mitigation
of the effect of noise on power supply has become a major design consideration
in clocking circuits. Rapid scaling of CMOS technology mandates the
design...
The increasing popularity of cellular phones with integrated cameras in the
recent past has led to major improvements in its image quality. However, integration of new features, such as mobile email, video streaming, MP3 etc. tend to put the limitation on image quality as camera phone designers struggle to manage...
The exponential rate of advances in modern communication devices in the last several years have brought us higher levels of functionality and performance as well as reductions in physical size and power consumption. To continue this rate of advancement, next generation systems require wider bandwidth and higher resolution ADCs. Additionally,...
Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts.
In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the...
Multiple-input multiple-output (MIMO) antenna technology is promising
for high-speed wireless communications without increasing the transmission band-
width. Space time coding (STC) is a scheme that employs multiple antennas to
increase transmission rate or to improve transmission quality. STC is used widely
in mobile cellular networks, wireless local area networks (WLAN)...
The demand for portable electronic systems and the continued
down-scaling of device dimensions resulted in rapid improvement in
the performance of integrated systems. Several low-voltage design
techniques have been proposed to operate analog circuits with sub-1V
supply. However, these techniques require higher power consumption
to achieve large dynamic range while...
In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications.
So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s)....
Digital-to-analog converters (DACs) suffer from static and dynamic nonlinearity problems, which degrade their accuracy and performance. Mismatch errors in the analog components restrict the maximum achievable linearity.
This thesis presents various techniques for correcting these errors. It describes a correction process for the nonlinear behavior of DACs, on three different...