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Filtering by: Subject Integrated passive components -- Design and construction Remove constraint Subject: Integrated passive components -- Design and construction Degree Level Master's Remove constraint Degree Level: Master's

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  • Model and design of cmos phase-locked loop

    Creator:
    Shum, Daniel K.
    Abstract:
    This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an oscillating frequency of up to 1000 KHz and it is programmable by means of an external resistor and capacitor. The first topic to be...
    Resource Type:
    Masters Thesis
    Full Text:
    Model and design of cmos phase-locked loop AN ABSTRACT

  • Switched-current logic for digital circuit design

    Creator:
    Subramanian, Vivek
    Resource Type:
    Masters Thesis
    Full Text:
    . Hodges and G.H. Jackson, Analysis and Design of Digital Integrated Circuits, Mc Graw Hill, 1988. 46

  • A numerical study of the thermal performance for surface mounted and through-hole mounted integrated circuits

    Creator:
    Wang, Jyi-Ren
    Resource Type:
    Masters Thesis
    Full Text:
    Mounted and Through-Hole Mounted Integrated Circuits. AN ABSTRACT OF THE THESIS OF Jyi-Ren Wang for the

  • A low ground bounce CMOS off-chip driver design

    Creator:
    Zheng, Jieyin
    Abstract:
    With the advancement of technology, submicron CMOSonly process is available now for Application Specific Integrated Circuits (ASICs). The high integration leads to the need for high pin counts. However voltage supply and ground bounce due to many output drivers switching at the same time is becoming a major problem. In...
    Resource Type:
    Masters Thesis
    Full Text:
    2.3 Prolong the Rise and Fall Time 7 Chapter 3. Proposed Circuit Design 10 3.1 Introduction 10 3.2

  • Device characterization and analog circuit design for heterojunction FETs

    Creator:
    Wang, Binan
    Abstract:
    Present day data processing technology requires very high speed signal processing and data conversion rates. Traditionally, these circuits have been implemented in silicon MOS technology, whose high speed performance is limited, due to inherent material properties. Though relatively immature compared to silicon technology, GaAs integrated circuit technology appears to be...
    Resource Type:
    Masters Thesis
    Full Text:
    Device Characterization and Analog Circuit Design for

  • Analog integrated circuit design using GaAs C-HFETs

    Creator:
    Gupta, Rakhee
    Abstract:
    Present day data processing technology requires very high speed signal processing and data conversion rates. One such application which requires high speed is switched capacitor circuits used in Sigma-Delta modulators. A major active component of switched capacitor circuits is the monolithic operational amplifier(opamp). Because of the relatively poor speed performance...
    Resource Type:
    Masters Thesis
    Full Text:
    n and p HFET devices. The design issues for analog integrated circuits are discussed, and an

  • Low noise FSCL digital circuits for decimation filter

    Creator:
    Wong, Man Wa
    Abstract:
    A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
    Resource Type:
    Masters Thesis
    Full Text:
    filter 42 LIST OF TABLES Table Page 1 Comparison of a 4-bit CLA and 4-bit CSA 16 2 Design

  • A programmable BiCMOS transconductance-capacitor filter for high frequencies

    Creator:
    Beck, Jeffery S.
    Abstract:
    With advancements in CMOS technology, high speed analog circuits that were traditionally implemented with discrete circuit components can now be made monolithically. Antialiasing filters for video signals as well as signal conditioning filters in high speed communication channels are examples of applications where high frequency integrated circuits are now feasible....
    Resource Type:
    Masters Thesis
    Full Text:
    . THE FOURTH-ORDER PROGRAMMABLE FILTER 47 4.1 Filter Topology and Component Selection 47 4.2 Simulation

  • The low-power design of prefix adder

    Creator:
    Chang, Che-jen
    Abstract:
    Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In...
    Resource Type:
    Masters Thesis
    Full Text:
    index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32

  • Low-voltage switched-capacitor circuits

    Creator:
    Bidari, Emad
    Abstract:
    In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material...
    Resource Type:
    Masters Thesis
    Full Text:
    and constructive critiques that put me a step ahead in understanding analog circuit design. I thank

  • Power estimation of superscalar microprocessor using VHDL model

    Creator:
    Zhang, Wanpeng
    Abstract:
    Power optimization becomes more and more important due to the design cost and reliability. Sometimes high power consumption means expensive package cost and low reliability. The first step in optimizing power consumption is determining where power is consumed within a processor. While system-level code tracing and bit transition calculation are...
    Resource Type:
    Masters Thesis
    Full Text:
    important due to the design cost and reliability. Sometimes high power consumption means expensive package

  • Analysis of planar multi-conductor multilayered structures by network analog method

    Creator:
    McVeety, Joseph J.
    Abstract:
    In this thesis the network analog method is used to analyze various planar multi-conductor structures in multilayered, lossy dielectric media. The method is based on an efficient impedance network representation of the finite difference approximation of Laplace's equation for the electric potential. Using the network analog method, the transmission line...
    Resource Type:
    Masters Thesis
    Full Text:
    lossy. Examples include multilayered printed circuit boards and silicon integrated circuits. These

  • Substrate coupling macromodel for lightly doped CMOS processes

    Creator:
    Koteeswaran, Mohanalakshmi
    Abstract:
    A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
    Resource Type:
    Masters Thesis
    Full Text:
    sensitive analog and RF circuits. The nOise coupling can be eliminated by improved circuit design [1, 2

  • Analysis and modeling of single-ended and differential spiral inductors in silicon-based RFICs

    Creator:
    Watson, Adam C.
    Abstract:
    A new comprehensive wide-band compact modeling methodology for single-ended spiral inductors and differential spiral inductors is presented. The new modeling methodology creates an equivalent circuit model consisting of frequency-independent circuit elements for use in circuit simulators. A fast automated extraction procedure is developed for determining the circuit element values from...
    Resource Type:
    Masters Thesis
    Full Text:
    creation of "System on Chip" (SoC) and "Application Specific Integrated Circuits" (ASIC). The SoC design

  • Analysis and modeling of multi-mode effects in coplanar waveguide bends

    Creator:
    Senguttuvan, Rajarajan
    Abstract:
    A novel method for modeling bends in coplanar waveguides (CPWs) is described. The CPW can be viewed as a pair of parallel coupled quasi-slot lines. Bends in the CPW are modeled as a non-uniform coupled line system in terms of their even- and odd- mode characteristics. This modeling approach is...
    Resource Type:
    Masters Thesis
    Full Text:
    flexibility in the design of CPWs for RF circuits and integration with other components on the circuit board

  • Electrical recommendations and formulas for metal fill in radio-frequency integrated circuits

    Creator:
    Gaskill, Steven
    Abstract:
    With increasing transistor operating frequencies, interconnects and passive devices are becoming performance limiters in integrated circuit (IC) designs. To combat this, the interconnect layers above the active silicon are trending toward low-κ dielectrics and Cu metallization. The use of these new materials has popularized chemical mechanical polishing (CMP) to planarize...
    Resource Type:
    Masters Thesis
    Full Text:
    Recommendations and Formulas for Metal Fill in Radio-Frequency Integrated Circuits Abstract approved: Andreas

  • Metal fill considerations for on-chip interconnects and spiral inductors

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically...
    Resource Type:
    Masters Thesis
    Full Text:
    advancements in integrated circuits (IC) technologies, design, and fabri- cation have significantly improved

  • Ultra low capacitance RFIC probe

    Creator:
    Jacob, Michael E.
    Abstract:
    In Radio Frequency Integrated Circuits (RFIC) or high frequency digital ICs, there is a demand to probe the internal nodes for testing. The ultra low capacitance RFIC probe presented in his work is a flexible tool for these applications. The probe utilizes the coupling between a tungsten needle and the...
    Resource Type:
    Masters Thesis
    Full Text:
    performance. Chapter three (RFIC Probe Design) discusses the design procedure. Construction details and

  • Design of compact folded-line RF power dividers

    Creator:
    Lim, Chi-young
    Abstract:
    Embedded passives in multi-layer media have gained importance for offering an attractive solution to the implementation of off-chip passive components in RF and mixed signal circuits, especially for wireless applications. Among the passive devices, power dividers and combiners are extensively used for a host of applications including balanced mixers, phase...
    Resource Type:
    Masters Thesis

  • An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

    Creator:
    Farahbakhshian, Farhad
    Abstract:
    An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
    Resource Type:
    Masters Thesis
    Full Text:
    (WPAN) [1], and wireless sensor networks [2], require low-power RF integrated circuit designs to reduce

  • Zinc tin oxide thin-film transistor circuits

    Creator:
    Heineck, Daniel Philip
    Abstract:
    The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.8 Integrated circuit E-mode TFT log(ID)-VGS transfer curves and mobility plots . . . 70 5.9 ID

  • Low voltage techniques for pipelined analog-to-digital converters

    Creator:
    Carnes, Joshua Kenneth
    Abstract:
    To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a...
    Resource Type:
    Masters Thesis
    Full Text:
    and low voltage design issues for pipelined ADCs and proposes a fully-differential implementation of

  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    , there is a desire to combine the PLL circuitry and other system components onto a single integrated

  • Low power scheduling schemes that consider latency and resource constraints at multiple voltages

    Creator:
    Huang, Shyh-Sen
    Abstract:
    Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources...
    Resource Type:
    Masters Thesis
    Full Text:
    FIGURES Figure Page 1. Design Flow and the Levels of Abstraction

  • Noise optimization for low-voltage CMOS audio preamplifier systems

    Creator:
    Brown, Matthew Eugene
    Abstract:
    There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of...
    Resource Type:
    Masters Thesis
    Full Text:
    required to minimize both the number of integrated circuits and off-chip discrete components. With supply